Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.4.13 NVIC_ICPR0 Register (Offset = 280h) [reset = X]
NVIC_ICPR0 is shown in
and described in
.
Irq 0 to 31 Clear Pending This register is used to clear pending interrupts and determine which interrupts
are currently pending.
are currently pending.
Figure 2-83. NVIC_ICPR0 Register
31
30
29
28
27
26
25
24
CLRPEND31
CLRPEND30
CLRPEND29
CLRPEND28
CLRPEND27
CLRPEND26
CLRPEND25
CLRPEND24
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
23
22
21
20
19
18
17
16
CLRPEND23
CLRPEND22
CLRPEND21
CLRPEND20
CLRPEND19
CLRPEND18
CLRPEND17
CLRPEND16
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
15
14
13
12
11
10
9
8
CLRPEND15
CLRPEND14
CLRPEND13
CLRPEND12
CLRPEND11
CLRPEND10
CLRPEND9
CLRPEND8
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
CLRPEND7
CLRPEND6
CLRPEND5
CLRPEND4
CLRPEND3
CLRPEND2
CLRPEND1
CLRPEND0
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-109. NVIC_ICPR0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
CLRPEND31
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV
for details). Reading the bit returns its current state.
30
CLRPEND30
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV
for details). Reading the bit returns its current state.
29
CLRPEND29
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV
for details). Reading the bit returns its current state.
28
CLRPEND28
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV
for details). Reading the bit returns its current state.
27
CLRPEND27
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV
for details). Reading the bit returns its current state.
26
CLRPEND26
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV
for details). Reading the bit returns its current state.
25
CLRPEND25
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV
for details). Reading the bit returns its current state.
24
CLRPEND24
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV
for details). Reading the bit returns its current state.
23
CLRPEND23
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV
for details). Reading the bit returns its current state.
22
CLRPEND22
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV
for details). Reading the bit returns its current state.
21
CLRPEND21
R/W
X
Writing 0 to this bit has no effect, writing 1 to this bit clears the
corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV
for details). Reading the bit returns its current state.
corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV
for details). Reading the bit returns its current state.
149
SWCU117A – February 2015 – Revised March 2015
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