Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.4.16 NVIC_IABR1 Register (Offset = 304h) [reset = X]
NVIC_IABR1 is shown in
and described in
.
Irq 32 to 63 Active Bit This register is used to determine which interrupts are active. Each flag in the
register corresponds to one interrupt.
register corresponds to one interrupt.
Figure 2-86. NVIC_IABR1 Register
31
30
29
28
27
26
25
24
RESERVED
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
ACTIVE33
ACTIVE32
R-X
R-X
R-X
Table 2-112. NVIC_IABR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-2
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
1
ACTIVE33
R
X
Reading 0 from this bit implies that interrupt line 33 is not active.
Reading 1 from this bit implies that the interrupt line 33 is active (See
EVENT:CPUIRQSEL33.EV for details).
Reading 1 from this bit implies that the interrupt line 33 is active (See
EVENT:CPUIRQSEL33.EV for details).
0
ACTIVE32
R
X
Reading 0 from this bit implies that interrupt line 32 is not active.
Reading 1 from this bit implies that the interrupt line 32 is active (See
EVENT:CPUIRQSEL32.EV for details).
Reading 1 from this bit implies that the interrupt line 32 is active (See
EVENT:CPUIRQSEL32.EV for details).
156
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated