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Cortex-M3 Processor Registers
2.7.4.18 NVIC_IPR1 Register (Offset = 404h) [reset = X]
NVIC_IPR1 is shown in
and described in
.
Irq 4 to 7 Priority This register is used to assign a priority from 0 to 255 to each of the available interrupts.
0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers
changes based on the setting in AIRCR.PRIGROUP.
0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority Registers
changes based on the setting in AIRCR.PRIGROUP.
Figure 2-88. NVIC_IPR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_7
PRI_6
PRI_5
PRI_4
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-114. NVIC_IPR1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_7
R/W
X
Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details).
23-16
PRI_6
R/W
X
Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details).
15-8
PRI_5
R/W
X
Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details).
7-0
PRI_4
R/W
X
Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details).
158
SWCU117A – February 2015 – Revised March 2015
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