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Cortex-M3 Processor Registers
2.7.4.20 NVIC_IPR3 Register (Offset = 40Ch) [reset = X]
NVIC_IPR3 is shown in
and described in
.
Irq 12 to 15 Priority This register is used to assign a priority from 0 to 255 to each of the available
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
interrupts. 0 is the highest priority, and 255 is the lowest. The interpretation of the Interrupt Priority
Registers changes based on the setting in AIRCR.PRIGROUP.
Figure 2-90. NVIC_IPR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRI_15
PRI_14
PRI_13
PRI_12
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-116. NVIC_IPR3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
PRI_15
R/W
X
Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details).
23-16
PRI_14
R/W
X
Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details).
15-8
PRI_13
R/W
X
Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details).
7-0
PRI_12
R/W
X
Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details).
160
SWCU117A – February 2015 – Revised March 2015
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