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Cortex-M3 Processor Registers
2.7.4.29 AIRCR Register (Offset = D0Ch) [reset = X]
AIRCR is shown in
and described in
.
Application Interrupt/Reset Control This register is used to determine data endianness, clear all active
state information for debug or to recover from a hard failure, execute a system reset, alter the priority
grouping position (binary point).
state information for debug or to recover from a hard failure, execute a system reset, alter the priority
grouping position (binary point).
Figure 2-99. AIRCR Register
31
30
29
28
27
26
25
24
VECTKEY
R/W-FA05h
23
22
21
20
19
18
17
16
VECTKEY
R/W-FA05h
15
14
13
12
11
10
9
8
ENDIANESS
RESERVED
PRIGROUP
R-X
R-X
R/W-X
7
6
5
4
3
2
1
0
RESERVED
SYSRESETRE
VECTCLRACTI
VECTRESET
Q
VE
R/W-X
W-X
W-X
W-X
Table 2-125. AIRCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
VECTKEY
R/W
FA05h
Register key. Writing to this register (AIRCR) requires 0x05FA in
VECTKEY. Otherwise the write value is ignored. Read always
returns 0xFA05.
VECTKEY. Otherwise the write value is ignored. Read always
returns 0xFA05.
15
ENDIANESS
R
X
Data endianness bit
0h = Little endian
1h = Big endian
14-11
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
10-8
PRIGROUP
R/W
X
Interrupt priority grouping field. This field is a binary point position
indicator for creating subpriorities for exceptions that share the same
pre-emption level. It divides the PRI_n field in the Interrupt Priority
Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-
emption level and a subpriority level. The binary point is a left-of
value. This means that the PRIGROUP value represents a point
starting at the left of the Least Significant Bit (LSB). The lowest value
might not be 0 depending on the number of bits allocated for
priorities, and implementation choices.
indicator for creating subpriorities for exceptions that share the same
pre-emption level. It divides the PRI_n field in the Interrupt Priority
Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-
emption level and a subpriority level. The binary point is a left-of
value. This means that the PRIGROUP value represents a point
starting at the left of the Least Significant Bit (LSB). The lowest value
might not be 0 depending on the number of bits allocated for
priorities, and implementation choices.
7-3
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
SYSRESETREQ
W
X
Requests a warm reset. Setting this bit does not prevent Halting
Debug from running.
Debug from running.
1
VECTCLRACTIVE
W
X
Clears all active state information for active NMI, fault, and
interrupts. It is the responsibility of the application to reinitialize the
stack. This bit is for returning to a known state during debug. The bit
self-clears. IPSR is not cleared by this operation. So, if used by an
application, it must only be used at the base level of activation, or
within a system handler whose active bit can be set.
interrupts. It is the responsibility of the application to reinitialize the
stack. This bit is for returning to a known state during debug. The bit
self-clears. IPSR is not cleared by this operation. So, if used by an
application, it must only be used at the base level of activation, or
within a system handler whose active bit can be set.
0
VECTRESET
W
X
System Reset bit. Resets the system, with the exception of debug
components. This bit is reserved for debug use and can be written to
1 only when the core is halted. The bit self-clears. Writing this bit to
1 while core is not halted may result in unpredictable behavior.
components. This bit is reserved for debug use and can be written to
1 only when the core is halted. The bit self-clears. Writing this bit to
1 while core is not halted may result in unpredictable behavior.
169
SWCU117A – February 2015 – Revised March 2015
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