Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.4.30 SCR Register (Offset = D10h) [reset = X]
SCR is shown in
and described in
.
System Control This register is used for power-management functions, i.e., signaling to the system when
the processor can enter a low power state, controlling how the processor enters and exits low power
states.
the processor can enter a low power state, controlling how the processor enters and exits low power
states.
Figure 2-100. SCR Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
RESERVED
R/W-X
15
14
13
12
11
10
9
8
RESERVED
R/W-X
7
6
5
4
3
2
1
0
RESERVED
SEVONPEND
RESERVED
SLEEPDEEP
SLEEPONEXIT
RESERVED
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-126. SCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-5
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
4
SEVONPEND
R/W
X
Send Event on Pending bit: 0: Only enabled interrupts or events can
wakeup the processor, disabled interrupts are excluded 1: Enabled
events and all interrupts, including disabled interrupts, can wakeup
the processor. When an event or interrupt enters pending state, the
event signal wakes up the processor from WFE. If the processor is
not waiting for an event, the event is registered and affects the next
WFE. The processor also wakes up on execution of an SEV
instruction.
wakeup the processor, disabled interrupts are excluded 1: Enabled
events and all interrupts, including disabled interrupts, can wakeup
the processor. When an event or interrupt enters pending state, the
event signal wakes up the processor from WFE. If the processor is
not waiting for an event, the event is registered and affects the next
WFE. The processor also wakes up on execution of an SEV
instruction.
3
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
2
SLEEPDEEP
R/W
X
Controls whether the processor uses sleep or deep sleep as its low
power mode
power mode
0h = Sleep
1h = Deep sleep
1
SLEEPONEXIT
R/W
X
Sleep on exit when returning from Handler mode to Thread mode.
Enables interrupt driven applications to avoid returning to empty
main application. 0: Do not sleep when returning to thread mode 1:
Sleep on ISR exit
Enables interrupt driven applications to avoid returning to empty
main application. 0: Do not sleep when returning to thread mode 1:
Sleep on ISR exit
0
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
170
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated