Texas Instruments CC2650DK Benutzerhandbuch
VIMS Registers
7.3.2 CTL Register (Offset = 4h) [reset = X]
CTL is shown in
and described in
Control Configure VIMS mode and line buffer settings
Figure 7-10. CTL Register
31
30
29
28
27
26
25
24
STATS_CLR
STATS_EN
DYN_CG_EN
RESERVED
R/W-X
R/W-X
R/W-X
R-X
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
RESERVED
R-X
7
6
5
4
3
2
1
0
RESERVED
IDCODE_LB_D SYSBUS_LB_D
ARB_CFG
PREF_EN
MODE
IS
IS
R-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 7-4. CTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31
STATS_CLR
R/W
X
Set this bit to clear statistic counters.
30
STATS_EN
R/W
X
Set this bit to enable statistic counters.
29
DYN_CG_EN
R/W
X
0: The in-built clock gate functionality is bypassed. 1: The in-built
clock gate functionality is enabled, automatically gating the clock
when not needed.
clock gate functionality is enabled, automatically gating the clock
when not needed.
28-6
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
5
IDCODE_LB_DIS
R/W
X
Icode/Dcode flash line buffer control 0: Enable 1: Disable
4
SYSBUS_LB_DIS
R/W
X
Sysbus flash line buffer control 0: Enable 1: Disable
3
ARB_CFG
R/W
X
Icode/Dcode and sysbus arbitation scheme 0: Static arbitration
(icode/docde > sysbus) 1: Round-robin arbitration
(icode/docde > sysbus) 1: Round-robin arbitration
2
PREF_EN
R/W
X
Tag prefetch control 0: Disabled 1: Enabled
1-0
MODE
R/W
X
VIMS mode request
0h = GPRAM : VIMS GPRAM mode
1h = CACHE : VIMS Cache mode
2h = VIMS Split Cache mode
3h = VIMS Off mode
539
SWCU117A – February 2015 – Revised March 2015
Versatile Instruction Memory System (VIMS)
Copyright © 2015, Texas Instruments Incorporated