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AES Cryptoprocessor Overview
10.1.4.5.2 AES Initialization Vector (IV) Registers
The AES Initialization Vector registers are used to provide and read the IV from the AES engine.
Table 10-6. Table 39AES Initialization Vector Registers
AES_IV_0, (Read/Write), 32-bit Address Offset: 0x540
AES_IV_1, (Read/Write), 32-bit Address Offset: 0x544
AES_IV_2, (Read/Write), 32-bit Address Offset: 0x548
AES_IV_1, (Read/Write), 32-bit Address Offset: 0x544
AES_IV_2, (Read/Write), 32-bit Address Offset: 0x548
AES_IV_3, (Read/Write), 32-bit Address Offset: 0x54C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AES_IV[31:0] AES_IV[63:32] AES_IV[95:64] AES_IV[127:96]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Initialization Vector, used for regular non-ECB modes (CBC/CTR):
Bit
Name
Description
127:0
AES_IV
For regular AES operations (CBC and CTR), these registers must be written with a
new 128-bit IV.
new 128-bit IV.
After an operation, these registers contain the latest 128-bit result IV, generated by the
crypto core.
crypto core.
If CTR mode is selected, this value is incremented with 0x1 - after first use - when a
new data block is submitted to the engine
new data block is submitted to the engine
Initialization Vector, used for CCM:
Bit
Name
Description
127:0
A0
For CCM, this field must be written with value A0, this value is the concatenation of:
A0-flags (5-bits of zero and 3-bits "L"), nonce and counter value.
"L" must be a copy from the "L" value of the AESCTL register. This "L" indicates the
width of the nonce and counter.
width of the nonce and counter.
The loaded counter must be initialized to zero.
The total width of A0 is 128-bit.
Initialization Vector, used for CBC-MAC:
Bit
Name
Description
127:0
Zeroes
For CBC-MAC this register must be written with zeroes at the start of each operation.
After an operation, these registers contain the 128-bit TAG output, generated by the
crypto core.
After an operation, these registers contain the 128-bit TAG output, generated by the
crypto core.
10.1.4.5.3 AES I/O Buffer Control, Mode, and Length Registers
The I/O buffer and mode-control register, AESCTL, specify the mode of operation for the AES engine.
NOTE:
Internal operation of the AES module can be interrupted by writing all mode bits to zero and
writing zeroes to the length registers ([AESDATALEN0], [AESDATALEN1], and
[AESAUTHLEN]).
[AESAUTHLEN]).
The length registers write the length values to the AES module. While processing, the length values
decrement to zero. If both lengths are zero, the data stream is finished and a new context is requested.
For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need
to be processed with the same key. Writing a zero length results in continued data requests until a new
context is written. For the other modes (CBC-MAC and CCM), no new data requests are done if the length
decrements to or equals zero.
decrement to zero. If both lengths are zero, the data stream is finished and a new context is requested.
For basic AES modes (ECB, CBC, and CTR), a crypto length of 0 can be written if multiple streams need
to be processed with the same key. Writing a zero length results in continued data requests until a new
context is written. For the other modes (CBC-MAC and CCM), no new data requests are done if the length
decrements to or equals zero.
It is advised to write a new length per packet. If the length registers decrement to zero, no new data is
processed until a new context or length value is written.
processed until a new context or length value is written.
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SWCU117A – February 2015 – Revised March 2015
Cryptography
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