Texas Instruments CC2650DK Benutzerhandbuch
AES Cryptoprocessor Overview
10.1.4.5.5 TAG Registers
The TAG registers buffer the TAG from the AES module and can be accessed through DMA or directly
with host reads. The TAG registers are shared with the intermediate authentication result registers, but
cannot be read until the processing is finished. While processing, a read from these registers returns
zeroes. If an operation does not return a TAG, reading from these registers returns an initialization vector
(IV). If an operation returns a TAG plus an IV and both need to be read by the host, the host must first
read the TAG followed by the IV. Reading these in reverse order returns the IV twice.
with host reads. The TAG registers are shared with the intermediate authentication result registers, but
cannot be read until the processing is finished. While processing, a read from these registers returns
zeroes. If an operation does not return a TAG, reading from these registers returns an initialization vector
(IV). If an operation returns a TAG plus an IV and both need to be read by the host, the host must first
read the TAG followed by the IV. Reading these in reverse order returns the IV twice.
For a host-rad operation, these registers contain the last 128-bit TAG output of the AES core. The TAG is
available until the next context is written. This register only contains valid data if the TAG is available, and
when SAVED_CONETXT_RDY bit in the AESCTL is set. During processing or for operations and modes
that do not return a TAG, reads from this register return data from the IV register.
available until the next context is written. This register only contains valid data if the TAG is available, and
when SAVED_CONETXT_RDY bit in the AESCTL is set. During processing or for operations and modes
that do not return a TAG, reads from this register return data from the IV register.
Table 10-8. AES Tag Output Register
AESTAGOUT__0 - AESTAGOUT__3, (Read Only), 32-bit Address Offset: 0x570 -0x57C in 0x4 byte increments
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
AES_TAG[31:0] AES_TAG[63:32] AES_TAG[95:64] AES_TAG[127:96]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
For CCM, CBC-MAC:
Bit
Field Name
Description
This register contains the authentication TAG for the
31:0
TAG
combined and authentication-only modes.
10.1.4.6 Key Area Registers
The local-key storage module is directly connected to 1-Kb memory. The module is capable of storing up
to eight AES keys and has eight 128-bit entries. The key size is programmed in the key store module. The
key material in the key store is not accessible through read operations through the AHB master and slave
interfaces.
to eight AES keys and has eight 128-bit entries. The key size is programmed in the key store module. The
key material in the key store is not accessible through read operations through the AHB master and slave
interfaces.
Keys can only be written to the key store through DMA. Once a DMA operation for a key read is started,
all received data is written to the key store module. Keys that are stored in the key store memory can only
be transferred to the AES key registers and are not accessible for any other purpose.
all received data is written to the key store module. Keys that are stored in the key store memory can only
be transferred to the AES key registers and are not accessible for any other purpose.
10.1.4.6.1 Key Write Area Register
The Key Write Area register defines where the keys should be written in the key store RAM. After writing
the Key Write Area register, the key store module is ready to receive the keys using a DMA operation. If
the key data transfer triggered an error in the key store, the error will be available in the interrupt status
register, [IRQSTAT], after the DMA is finished. The key store write-error, KEY_ST_WR_ERR, is asserted
when the programmed or selected area is not completely written. This error is also asserted when the
DMA operation writes to ram areas that are not selected.
the Key Write Area register, the key store module is ready to receive the keys using a DMA operation. If
the key data transfer triggered an error in the key store, the error will be available in the interrupt status
register, [IRQSTAT], after the DMA is finished. The key store write-error, KEY_ST_WR_ERR, is asserted
when the programmed or selected area is not completely written. This error is also asserted when the
DMA operation writes to ram areas that are not selected.
10.1.4.6.2 Key Written Area Register
The Key Written Area register shows which areas of the key store RAM contain valid written keys.
When a new key must be written to the key store on a location that is already occupied by a valid key, this
key area must be cleared first. Clear the key area by writing this register before the new key is written to
the key store memory.
key area must be cleared first. Clear the key area by writing this register before the new key is written to
the key store memory.
Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
10.1.4.6.3 Key Size Register
The Key Size register defines the size of the keys that are written with DMA. The Key Size register should
be configured before writing to the [KEYWRITEAREA] register.
be configured before writing to the [KEYWRITEAREA] register.
809
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated