Texas Instruments CC2650DK Benutzerhandbuch
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Set-up and initialization
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Data processing
‘Full processing’
AES Cryptoprocessor Overview
10.1.4.6.4 Key Read Area Register
The Key Read Area register selects the key store RAM area from where the key needs to be read that is
used for an AES operation. The operation starts directly after writing this register. When the operation is
finished, the status of the key store read operation is available in the interrupt status register IRQSTAT.
Key store read error asserts when a ram area is selected that does not contain a valid written key
used for an AES operation. The operation starts directly after writing this register. When the operation is
finished, the status of the key store read operation is available in the interrupt status register IRQSTAT.
Key store read error asserts when a ram area is selected that does not contain a valid written key
10.1.5 Performance
10.1.5.1 Introduction
The processing steps of the AES module are the basis for the performance calculations. The following
three major steps are identified for crypto operations using DMA:
three major steps are identified for crypto operations using DMA:
1. Initialization (setup and initialization of the engines, DMA, and so forth)
2. Data processing for the complete message
3. Finalization (reading out the result, status checking)
The orange sections (full processing) of
, are covered by step one and step three. Steps one
and three are under control of the host CPU, and therefore dependent on the performance of the host.
The second step is covered by the green section (data processing), and is fully handled by the hardware,
which is not dependent on the performance of the host CPU.
The second step is covered by the green section (data processing), and is fully handled by the hardware,
which is not dependent on the performance of the host CPU.
Figure 10-2. Symmetric Crypto Processing Steps
The full processing part is required once per processing command, and precedes the processing of the
first data block. The data processing blocks depend on the amount of data to be processed by the
command. The finalization is required when the operation produces a result digest or TAG.
first data block. The data processing blocks depend on the amount of data to be processed by the
command. The finalization is required when the operation produces a result digest or TAG.
The number of required blocks is determined by the block size requirements of the algorithms selected by
the command. The AES block size is 128 bits.
the command. The AES block size is 128 bits.
For longer data streams, the data processing time approaches the theoretical maximum throughput. For
operations that use the slave interface as alternative for the DMA, the performance depends on the
performance of the host CPU.
operations that use the slave interface as alternative for the DMA, the performance depends on the
performance of the host CPU.
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SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated