Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.1.33 TER Register (Offset = E00h) [reset = X]
TER is shown in
and described in
Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding
stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are
accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged
access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as
required.
stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are
accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged
access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as
required.
Figure 2-36. TER Register
31
30
29
28
27
26
25
24
STIMENA31
STIMENA30
STIMENA29
STIMENA28
STIMENA27
STIMENA26
STIMENA25
STIMENA24
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
23
22
21
20
19
18
17
16
STIMENA23
STIMENA22
STIMENA21
STIMENA20
STIMENA19
STIMENA18
STIMENA17
STIMENA16
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
15
14
13
12
11
10
9
8
STIMENA15
STIMENA14
STIMENA13
STIMENA12
STIMENA11
STIMENA10
STIMENA9
STIMENA8
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
7
6
5
4
3
2
1
0
STIMENA7
STIMENA6
STIMENA5
STIMENA4
STIMENA3
STIMENA2
STIMENA1
STIMENA0
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-59. TER Register Field Descriptions
Bit
Field
Type
Reset
Description
31
STIMENA31
R/W
X
Bit mask to enable tracing on ITM stimulus port 31.
30
STIMENA30
R/W
X
Bit mask to enable tracing on ITM stimulus port 30.
29
STIMENA29
R/W
X
Bit mask to enable tracing on ITM stimulus port 29.
28
STIMENA28
R/W
X
Bit mask to enable tracing on ITM stimulus port 28.
27
STIMENA27
R/W
X
Bit mask to enable tracing on ITM stimulus port 27.
26
STIMENA26
R/W
X
Bit mask to enable tracing on ITM stimulus port 26.
25
STIMENA25
R/W
X
Bit mask to enable tracing on ITM stimulus port 25.
24
STIMENA24
R/W
X
Bit mask to enable tracing on ITM stimulus port 24.
23
STIMENA23
R/W
X
Bit mask to enable tracing on ITM stimulus port 23.
22
STIMENA22
R/W
X
Bit mask to enable tracing on ITM stimulus port 22.
21
STIMENA21
R/W
X
Bit mask to enable tracing on ITM stimulus port 21.
20
STIMENA20
R/W
X
Bit mask to enable tracing on ITM stimulus port 20.
19
STIMENA19
R/W
X
Bit mask to enable tracing on ITM stimulus port 19.
18
STIMENA18
R/W
X
Bit mask to enable tracing on ITM stimulus port 18.
17
STIMENA17
R/W
X
Bit mask to enable tracing on ITM stimulus port 17.
16
STIMENA16
R/W
X
Bit mask to enable tracing on ITM stimulus port 16.
15
STIMENA15
R/W
X
Bit mask to enable tracing on ITM stimulus port 15.
14
STIMENA14
R/W
X
Bit mask to enable tracing on ITM stimulus port 14.
13
STIMENA13
R/W
X
Bit mask to enable tracing on ITM stimulus port 13.
12
STIMENA12
R/W
X
Bit mask to enable tracing on ITM stimulus port 12.
11
STIMENA11
R/W
X
Bit mask to enable tracing on ITM stimulus port 11.
10
STIMENA10
R/W
X
Bit mask to enable tracing on ITM stimulus port 10.
84
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated