Texas Instruments CC2650DK Benutzerhandbuch
Cortex-M3 Processor Registers
2.7.1.35 TCR Register (Offset = E80h) [reset = X]
TCR is shown in
and described in
.
Trace Control Use this register to configure and control ITM transfers. This register can only be written in
privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is
controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is
controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
Figure 2-38. TCR Register
31
30
29
28
27
26
25
24
RESERVED
R/W-X
23
22
21
20
19
18
17
16
BUSY
ATBID
R/W-X
R/W-X
15
14
13
12
11
10
9
8
RESERVED
TSPRESCALE
R/W-X
R/W-X
7
6
5
4
3
2
1
0
RESERVED
SWOENA
DWTENA
SYNCENA
TSENA
ITMENA
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Table 2-61. TCR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
23
BUSY
R/W
X
Set when ITM events present and being drained.
22-16
ATBID
R/W
X
Trace Bus ID for CoreSight system. Optional identifier for multi-
source trace stream formatting. If multi-source trace is in use, this
field must be written with a non-zero value.
source trace stream formatting. If multi-source trace is in use, this
field must be written with a non-zero value.
15-10
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
9-8
TSPRESCALE
R/W
X
Timestamp prescaler
0h = No prescaling
1h = Divide by 4
2h = Divide by 16
3h = Divide by 64
7-5
RESERVED
R/W
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
4
SWOENA
R/W
X
Enables asynchronous clocking of the timestamp counter (when
TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable
asynchronous clocking of the timestamp counter. 0x0: Mode
disabled. Timestamp counter uses system clock from the core and
counts continuously. 0x1: Timestamp counter uses lineout (data
related) clock from TPIU interface. The timestamp counter is held in
reset while the output line is idle.
TSENA = 1). If TSENA = 0, writing this bit to 1 does not enable
asynchronous clocking of the timestamp counter. 0x0: Mode
disabled. Timestamp counter uses system clock from the core and
counts continuously. 0x1: Timestamp counter uses lineout (data
related) clock from TPIU interface. The timestamp counter is held in
reset while the output line is idle.
3
DWTENA
R/W
X
Enables the DWT stimulus (hardware event packet emission to the
TPIU from the DWT)
TPIU from the DWT)
2
SYNCENA
R/W
X
Enables synchronization packet transmission for a synchronous
TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the
correct synchronization speed.
TPIU. CPU_DWT:CTRL.SYNCTAP must be configured for the
correct synchronization speed.
87
SWCU117A – February 2015 – Revised March 2015
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