Freescale Semiconductor 56F8367 Evaluation Module MC56F8367EVME MC56F8367EVME Datenbogen

Architecture Block Diagram

Freescale Semiconductor

13

Preliminary

pdb_m[15:0]

Program data bus for instruction word fetches or read operations.

cdbw[15:0]

Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus 
are used for writes to program memory.)

pab[20:0]

Program memory address bus. Data is returned on pdb_m bus.

cdbr_m[31:0]

Primary core data bus for memory reads. Addressed via xab1 bus.

cdbw[31:0]

Primary core data bus for memory writes. Addressed via xab1 bus.

xab1[23:0]

Primary data address bus. Capable of addressing bytes

1

, words, and long data types. Data is written 

on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.

1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced

to 0.

xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.

xab2[23:0]

Secondary data address bus used for the second of two simultaneous accesses. Capable of 
addressing only words. Data is returned on xdb2_m.

IPBus [15:0]

Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate 
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.