Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
12-66
Freescale
Semiconductor
DDR SDRAM Memory Controller
—
20
0
Reserved. Write to zero for future compatibility.
32_BE
19
0
32-Bit Bus Enable
Selects bus size.
Selects bus size.
0
64-bit bus is used.
1
32-bit bus is used.
8_BE
18
0
8-Beat Burst Enable
Note:
Note:
DDR2 (SDRAM_TYPE = 011) must use
4-beat bursts, even when using 32-bit bus
mode; DDR3 (SDRAM_TYPE = 111) must
use 8-beat bursts when using 32-bit bus
mode. DDR3 must use 4 beat burst when
using 64-bit bus mode.
4-beat bursts, even when using 32-bit bus
mode; DDR3 (SDRAM_TYPE = 111) must
use 8-beat bursts when using 32-bit bus
mode. DDR3 must use 4 beat burst when
using 64-bit bus mode.
0
4-beat burst.
1
8-beat burst.
NCAP
17
0
Non-Concurrent Auto-Precharge
Some older DDR DRAMs do not support concurrent
auto precharge. If one of these devices is used, this
bit must be set if auto precharge is used.
Some older DDR DRAMs do not support concurrent
auto precharge. If one of these devices is used, this
bit must be set if auto precharge is used.
0
DRAMs in system support
concurrent auto-precharge.
concurrent auto-precharge.
1
DRAMs in system do not support
concurrent auto-precharge.
concurrent auto-precharge.
3T_EN
16
0
3T Timing Enable
Enables/disabled 3T timing. This field cannot be set if
DDR_SDRAM_CFG[2T_EN] is also set.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for three full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the third
cycle.
Enables/disabled 3T timing. This field cannot be set if
DDR_SDRAM_CFG[2T_EN] is also set.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for three full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the third
cycle.
0
1T timing is enabled if 2T_EN is
also cleared. The DRAM
command/address are held for
only 1 cycle on the DRAM bus.
also cleared. The DRAM
command/address are held for
only 1 cycle on the DRAM bus.
1
3T timing is enabled.
2T_EN
15
0
2T Timing Enable
Enables/disabled 2T timing.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for two full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the second
cycle.
Enables/disabled 2T timing.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for two full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the second
cycle.
0
1T timing is used if 3T_EN is also
cleared.
cleared.
1
2T timing is enabled.
BA_INTLV_CTL
14–8
0
Bank (chip select) interleaving control.
Set this field only if you wish to use bank interleaving.
Set this field only if you wish to use bank interleaving.
0000000 No external memory banks are
interleaved
1000000 External memory banks 0 and
1 are interleaved
—
7–4
0
Reserved. Write to zero for future compatibility.
HSE
3
0
Half-Strength Drive Enable
Specifies whether the I/O drivers are configured to full
strength or half strength. This bit applies only when
automatic driver compensation is disabled and the
software override for the driver strength is not used in
DDRCDR1 and 2.
Specifies whether the I/O drivers are configured to full
strength or half strength. This bit applies only when
automatic driver compensation is disabled and the
software override for the driver strength is not used in
DDRCDR1 and 2.
0
I/O drivers are configured to
full-strength.
full-strength.
1
IO drivers are configured to
half-strength.
half-strength.
—
2
0
Reserved. Write to zero for future compatibility.
Table 12-28. DDR_SDRAM_CFG Field Descriptions (Continued)
Bits
Reset Description
Settings