Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Memory Controller Programming Model
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-67
12.8.9
DDR SDRAM Control Configuration Register 2
(MnDDR_SDRAM_CFG_2)
(MnDDR_SDRAM_CFG_2)
MEM_HALT
1
0
DDR Memory Controller Halt
When this bit is set, the memory controller does not
accept any new transactions until the bit is cleared.
This bit can be used when initialization is bypassed
and the MODE REGISTER SET, EXTENDED MODE
REGISTER SET, EXTENDED MODE REGISTER2
SET and EXTENDED MODE REGISTER3 SET
commands are forced through software. This bit
should be used carefully.
Using this MHALT option can create congestion on
the system interconnection and can cause hangs of
the cores and other initiator.
When this bit is set, the memory controller does not
accept any new transactions until the bit is cleared.
This bit can be used when initialization is bypassed
and the MODE REGISTER SET, EXTENDED MODE
REGISTER SET, EXTENDED MODE REGISTER2
SET and EXTENDED MODE REGISTER3 SET
commands are forced through software. This bit
should be used carefully.
Using this MHALT option can create congestion on
the system interconnection and can cause hangs of
the cores and other initiator.
0
DDR controller accepts new
transactions.
transactions.
1
DDR controller finishes any
remaining transactions and then
halts until software clears this bit.
remaining transactions and then
halts until software clears this bit.
BI
0
0
Bypass Initialization
Specifies the conditions for initialization. When this bit
is set, software is responsible for initializing memory
through the DDR_SDRAM_MD_CNTL register. If
software is initializing memory, the MEM_HALT bit
can be set to prevent the DDR controller from issuing
transactions during the initialization sequence.
Note:
Specifies the conditions for initialization. When this bit
is set, software is responsible for initializing memory
through the DDR_SDRAM_MD_CNTL register. If
software is initializing memory, the MEM_HALT bit
can be set to prevent the DDR controller from issuing
transactions during the initialization sequence.
Note:
Note that the DDR controller does not issue
a DLL reset to the DRAMs when bypassing
the initialization routine, regardless of the
value of
DDR_SDRAM_CFG[DLL_RST_DIS]. If a
DLL reset is required, then the controller
should be forced to enter and exit self
refresh after the controller is enabled.
a DLL reset to the DRAMs when bypassing
the initialization routine, regardless of the
value of
DDR_SDRAM_CFG[DLL_RST_DIS]. If a
DLL reset is required, then the controller
should be forced to enter and exit self
refresh after the controller is enabled.
For details on avoiding ECC errors in this mode, see
the discussion of the DDR SDRAM Initialization
Address Register on page 12-76.
the discussion of the DDR SDRAM Initialization
Address Register on page 12-76.
0
DDR controller cycles through
the initialization routine based on
the value of SDRAM_Type.
the initialization routine based on
the value of SDRAM_Type.
1
Initialization routine is bypassed.
DDR_SDRAM_CFG_2 DDR SDRAM Control Configuration Register 2
Offset 0x0114
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
FRC_
SR
—
DLL_
RST_
DIS
—
DQS_CFG
—
ODT_CFG
—
Type
R/W
R
R/W
R
R/W
R
R/W
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NUM_PR
—
OBC_
CFG
AP_
EN
D_INIT
—
RCW_
EN
—
MD_
EB
Type
R/W
R
R/W
R
R/W
R
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 12-28. DDR_SDRAM_CFG Field Descriptions (Continued)
Bits
Reset Description
Settings