Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
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MSC8156EVM
MSC8156 Reference Manual, Rev. 2
12-68
Freescale
Semiconductor
DDR SDRAM Memory Controller
DDR_SDRAM_CFG_2 provides control configuration for the DDR controller in addition to that
provided by DDR_SDRAM_CFG.
provided by DDR_SDRAM_CFG.
Table 12-29. DDR_SDRAM_CFG_2 Field Descriptions
Bit Reset
Description
FRC_SR
31
0
Force Self Refresh
0
Normal operating mode.
1
Enter ‘Self Refresh mode.
—
30
0
Reserved. Write to zero for future compatibility.
DLL_RST_
DIS
29
0
DLL Reset Disable
The DDR controller typically issues a DLL reset to the
DRAMs when it exists self refresh. However, you can
disable this function by setting this bit during
initialization.
The DDR controller typically issues a DLL reset to the
DRAMs when it exists self refresh. However, you can
disable this function by setting this bit during
initialization.
0
DDR controller issues a DLL
reset when exiting self refresh.
reset when exiting self refresh.
1
DDR controller does not issue a
DLL reset when exiting self
refresh.
DLL reset when exiting self
refresh.
—
28
0
Reserved. Write to zero for future compatibility.
DQS_CFG
27–26
0
DQS Configuration
This bit must be programmed for proper operation.
This bit must be programmed for proper operation.
00
Reserved
01
Differential DQS signals are
used for DDR2 support.
used for DDR2 support.
10
Reserved.
11
Reserved.
—
25–23
0
Reserved. Write to zero for future compatibility.
ODT_CFG
22–21
0
ODT Configuration
Defines how ODT is driven to the on-chip I/O.
See Table 12-51 and Table 12-52 for the definition of
the impedance value that is used.
Defines how ODT is driven to the on-chip I/O.
See Table 12-51 and Table 12-52 for the definition of
the impedance value that is used.
00
Never assert ODT to internal
I/O.
I/O.
01
Assert ODT to internal I/O
only during writes to DRAM.
only during writes to DRAM.
10
Assert ODT to internal I/O
only during reads to DRAM.
only during reads to DRAM.
11
Always keep ODT asserted to
internal I/O.
internal I/O.
—
20–16
0
Reserved. Write to zero for future compatibility.
NUM_PR
15–12
0
Number of Posted Refreshes
Determines how many posted refreshes, if any, can be
issued at one time. If posted refreshes are used, this
field, along with DDR_SDRAM_INTERVAL[REFINT],
must be programmed so that the maximum t
Determines how many posted refreshes, if any, can be
issued at one time. If posted refreshes are used, this
field, along with DDR_SDRAM_INTERVAL[REFINT],
must be programmed so that the maximum t
ras
specification cannot be violated. For example, some
DDR SDRAMs cannot use more than three posted
refreshes because the required refresh interval can
exceed the maximum constraint for t
DDR SDRAMs cannot use more than three posted
refreshes because the required refresh interval can
exceed the maximum constraint for t
ras
.
Note: {TIMING_CFG_1[PRETOACT] +
[DDR_SDRAM_CFG_2[NUM_PR] *
({EXT_REFREC || REFREC} + 8 + 2)]} <<
DDR_SDRAM_INTERVAL[REFINT
[DDR_SDRAM_CFG_2[NUM_PR] *
({EXT_REFREC || REFREC} + 8 + 2)]} <<
DDR_SDRAM_INTERVAL[REFINT
0000
Reserved.
0001
1 refresh at a time.
0010
2 refreshes at a time.
0011
3 refreshes at a time.
0100
4 refreshes at a time.
0101
5 refresh at a time.
0110
6 refreshes at a time.
0111
7 refreshes at a time.
1000
8 refreshes at a time.
1001–1111Reserved.
—
11–7
0
Reserved. Write to zero for future compatibility.