Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Benutzerhandbuch
Produktcode
MSC8156EVM
Memory Controller Programming Model
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-69
OBC_CFG
6
0
On-The-Fly Burst Chop Configuration
Determines if on-the-fly Burst Chop is used. This bit
should only be set if DDR3 memories are used. If
on-the-fly Burst Chop mode is not used with DDR3
memories, then fixed Burst Chop mode may be used if
the proper turnaround times are programmed into
TIMING_CFG_0 and TIMING_CFG_4.
DDR_SDRAM_CFG[8_BE] should be cleared for both
on-the-fly Burst Chop mode or fixed Burst Chop mode
when using a 64-bit data bus with DDR3 memories.
Determines if on-the-fly Burst Chop is used. This bit
should only be set if DDR3 memories are used. If
on-the-fly Burst Chop mode is not used with DDR3
memories, then fixed Burst Chop mode may be used if
the proper turnaround times are programmed into
TIMING_CFG_0 and TIMING_CFG_4.
DDR_SDRAM_CFG[8_BE] should be cleared for both
on-the-fly Burst Chop mode or fixed Burst Chop mode
when using a 64-bit data bus with DDR3 memories.
0
On-the-fly Burst Chop mode is
disabled. Fixed burst lengths
defined in
DDR_SDRAM_CFG[8_BE] are
used. If fixed Burst Chop is used
(with DDR3 memories), then
DDR_SDRAM_CFG[8_BE]
should be cleared.
disabled. Fixed burst lengths
defined in
DDR_SDRAM_CFG[8_BE] are
used. If fixed Burst Chop is used
(with DDR3 memories), then
DDR_SDRAM_CFG[8_BE]
should be cleared.
1 On-the-fly Burst Chop mode is
used. DDR_SDRAM_CFG[8_BE]
should be cleared for on-the-fly
Burst Chop mode.
DDR_SDRAM_CFG[32-BE]
should also be cleared for
on-the-fly Burst Chop mode
should be cleared for on-the-fly
Burst Chop mode.
DDR_SDRAM_CFG[32-BE]
should also be cleared for
on-the-fly Burst Chop mode
AP_EN
5
0
Address Parity Enable
Determines whether to generate and check address
parity for the address and control signals when using
registered DIMMs. If address parity is used, the
MAPAR_OUT and MAPAR_IN pins are used to drive
the parity bit and to receive errors from the open-drain
parity error signal. Even parity are used, and parity is
generated for the MA[15–0], MBA[2–0], MRAS,
MCAS, MWE signals. Parity is not generated for the
MCKE[0–1], MODT[0–1], or MCS[0–1] signals.
Note:
Determines whether to generate and check address
parity for the address and control signals when using
registered DIMMs. If address parity is used, the
MAPAR_OUT and MAPAR_IN pins are used to drive
the parity bit and to receive errors from the open-drain
parity error signal. Even parity are used, and parity is
generated for the MA[15–0], MBA[2–0], MRAS,
MCAS, MWE signals. Parity is not generated for the
MCKE[0–1], MODT[0–1], or MCS[0–1] signals.
Note:
Address parity should not be used for
non-zero values of
TIMING_CFG_3[CNTL_ADJ].
non-zero values of
TIMING_CFG_3[CNTL_ADJ].
0
Address parity not used
1
Address parity used
D_INIT
4
0
DRAM Data Initialization
This bit is set by software, and it is cleared by
hardware. If software sets this bit before the memory
controller is enabled, the controller automatically
initializes DRAM after it is enabled. This bit is
automatically cleared by hardware once the
initialization is completed. This data initialization bit
should only be set when the controller is idle..
This bit is set by software, and it is cleared by
hardware. If software sets this bit before the memory
controller is enabled, the controller automatically
initializes DRAM after it is enabled. This bit is
automatically cleared by hardware once the
initialization is completed. This data initialization bit
should only be set when the controller is idle..
0
No data initialization, and no data
initialization is scheduled.
initialization is scheduled.
1
The memory controller initializes
memory when it is enabled.
memory when it is enabled.
—
3
0
Reserved. Write to zero for future compatibility.
RCW_EN
2
0
Register Control Word Enable
If DDR3 registered DIMMs are used, it may be
necessary to write the register control words before
issuing commands to DRAM. If this bit is set, the
controller writes the register control words after
DDR_SDRAM_CFG[MEM_EN] is set, unless
DDR_SDRAM_CFG[BI] is set. The register control
words are written with the values in
DDR_SDRAM_RCW_1 and DDR_SDRAM_RCW_2.
If DDR3 registered DIMMs are used, it may be
necessary to write the register control words before
issuing commands to DRAM. If this bit is set, the
controller writes the register control words after
DDR_SDRAM_CFG[MEM_EN] is set, unless
DDR_SDRAM_CFG[BI] is set. The register control
words are written with the values in
DDR_SDRAM_RCW_1 and DDR_SDRAM_RCW_2.
0
Register control words are not
automatically written during
DRAM initialization.
automatically written during
DRAM initialization.
1
Register control words are
automatically written during
DRAM initialization. This bit
should only be set if DDR3
registered DIMMs are used, and
the default settings need to be
modified.
automatically written during
DRAM initialization. This bit
should only be set if DDR3
registered DIMMs are used, and
the default settings need to be
modified.
—
1
0
Reserved. Write to zero for future compatibility.
Table 12-29. DDR_SDRAM_CFG_2 Field Descriptions (Continued)
Bit Reset
Description