Texas Instruments TURBO-DECODER COPROCESSOR 2 TMS320C6457 DSP Benutzerhandbuch
6.10 TCP2 Input Configuration Register 7 (TCPIC7)
Registers
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The TCP2 input configuration register 7 (TCPIC7) is shown in
and described in
.
TCPIC7 sets set the tail bits used by the TCP.
Figure 40. TCP2 Input Configuration Register 7 (TCPIC7)
31
18 17
0
Reserved
TAIL2
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TCP2 Input Configuration Register 7 (TCPIC7) Field Descriptions
Bit
Field
Value
Description
31-18
Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has
no effect.
no effect.
17-0
TAIL2
0-FFFF FFFFh
Tail bit. Values must be set as in the following list.
•
CDMA-2000 Tail Symbol Pattern for Code Rate 1/4
tail+2
tail+1
tail+0
p10
p10
p10
•
CDMA-2000 Tail Symbol Pattern for Code Rate 1/3 or 1/2
tail+2
tail+1
tail+0
p10
p10
p10
•
CDMA-2000 Tail Symbol Pattern for Code Rate 3/4
tail+2
tail+1
tail+0
0
0
p10
•
CDMA-2000 Tail Symbol Pattern for Code Rate 1/5 or 1/4
tail+2
tail+1
tail+0
p10
p10
p10
•
CDMA-2000 Tail Symbol Pattern for Code Rate 1/3, 1/2, or 3/4
tail+2
tail+1
tail+0
p10
p10
p10
TMS320C6457 Turbo-Decoder Coprocessor 2
34
SPRUGK1 – March 2009