Digi NS9750 Benutzerhandbuch
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E t h e r n e t C o m m u n i c a t i o n M o d u l e
Setting the EXTDMA (enable transmit DMA) bit in Ethernet General Control Register #1
starts the transfer of transmit frames from the system memory to the TX_FIFO. The
starts the transfer of transmit frames from the system memory to the TX_FIFO. The
TX_WR
logic reads the first buffer descriptor in the TX buffer descriptor RAM.
If the F bit is set, it transfers data from system memory to the TX_FIFO
using the buffer pointer as the starting point. This process continues until
the end of the buffer is reached. The address for each subsequent read of
the buffer is incremented by 32 bytes (that is,
using the buffer pointer as the starting point. This process continues until
the end of the buffer is reached. The address for each subsequent read of
the buffer is incremented by 32 bytes (that is,
0x20
). The buffer length field
in the buffer descriptor is decremented by this same value, each transfer,
to identify when the end of the buffer is reached.
to identify when the end of the buffer is reached.
If the L field in the buffer descriptor is 0, the next buffer descriptor in the
RAM continues the frame transfer until the L field in the current buffer
descriptor is 1. This identifies the current buffer as the last buffer of a
transmit frame.
RAM continues the frame transfer until the L field in the current buffer
descriptor is 1. This identifies the current buffer as the last buffer of a
transmit frame.
After the entire frame has been written to the TX_FIFO, the
TX_WR
logic waits for a
signal from the
TX_RD
logic indicating that frame transmission has completed at the
MAC. The
TX_WR
logic updates the buffer length, status, and F fields of the current
buffer descriptor (that is, the last buffer descriptor for the frame) in the TX buffer
descriptor RAM when the signal is received.
descriptor RAM when the signal is received.
The
TX_WR
logic examines the status received from the MAC after it has transmitted
the frame.
If the frame was transmitted successfully, the
TX_WR
logic sets
TXDONE
(frame transmission complete) in the Ethernet Interrupt Status register and
reads the next buffer descriptor. If a new frame is available (that is, the F
bit is set), the
reads the next buffer descriptor. If a new frame is available (that is, the F
bit is set), the
TX_WR
starts transferring the frame. If a new frame is not
available, the
TX_WR
logic sets the
TXIDLE
(
TX_WR
logic has no frame to
transmit) bit in the Ethernet Interrupt Status register and waits for the
software to toggle
software to toggle
TCLER
(clear transmit logic), in Ethernet General Control
Register #2, from low to high to resume processing. When TCLER is toggled,
transmission starts again with the buffer descriptor pointed to by the
Transmit Recover Buffer Descriptor Pointer register. Software should update
this register before toggling TCLER.
The Transmit Buffer Descriptor Pointer Offset register will be valid only if
the previous buffer completed normally. In the case of an error that
requires that software manually throw away a packet by clearing out buffer
descriptors, the Transmit Buffer Descriptor Pointer Offset register will not
transmission starts again with the buffer descriptor pointed to by the
Transmit Recover Buffer Descriptor Pointer register. Software should update
this register before toggling TCLER.
The Transmit Buffer Descriptor Pointer Offset register will be valid only if
the previous buffer completed normally. In the case of an error that
requires that software manually throw away a packet by clearing out buffer
descriptors, the Transmit Buffer Descriptor Pointer Offset register will not