Texas Instruments SM320F2812-HT Benutzerhandbuch
www.ti.com
SGUS062A – JUNE 2009 – REVISED APRIL 2010
List of Figures
2-1
SM320F2812 Die Layout
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2-2
SM320F2812 172-Pin HFG CQFP (Top View)
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3-1
Functional Block Diagram
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3-2
F2812 Memory Map (See Notes A. Through G.)
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3-3
External Interface Block Diagram
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3-4
Interrupt Sources
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3-5
Multiplexing of Interrupts Using the PIE Block
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3-6
Clock and Reset Domains
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3-7
OSC and PLL Block
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3-8
Recommended Crystal/Clock Connection
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3-9
Watchdog Module
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4-1
CPU-Timers
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4-2
CPU-Timer Interrupts Signals and Output Signal (See Notes A. and B.)
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4-3
Event Manager A Functional Block Diagram (See Note A.)
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4-4
Block Diagram of the F2812 ADC Module
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4-5
ADC Pin Connections With Internal Reference (See Notes A and B)
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4-6
ADC Pin Connections With External Reference
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4-7
eCAN Block Diagram and Interface Circuit
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4-8
eCAN Memory Map
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4-9
McBSP Module With FIFO
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4-10
Serial Communications Interface (SCI) Module Block Diagram
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4-11
Serial Peripheral Interface Module Block Diagram (Slave Mode)
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4-12
GPIO/Peripheral Pin Multiplexing
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5-1
28x Device Nomenclature
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6-1
SM320F2812-HT Life Expectancy Curve
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6-2
Typical Current Consumption Over Frequency
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6-3
Typical Power Consumption Over Frequency
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6-4
F2812 Typical Power-Up and Power-Down Sequence – Option 2
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6-5
Output Levels
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6-6
Input Levels
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6-7
3.3-V Test Load Circuit
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6-8
Clock Timing
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6-9
Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)
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6-10
Power-on Reset in Microprocessor Mode (XMP/MC = 1)
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6-11
Warm Reset in Microcomputer Mode
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6-12
Effect of Writing Into PLLCR Register
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6-13
IDLE Entry and Exit Timing
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6-14
STANDBY Entry and Exit Timing
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6-15
HALT Wakeup Using XNMI
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6-16
PWM Output Timing
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6-17
TDIRx Timing
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6-18
EVASOC Timing
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6-19
EVBSOC Timing
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6-20
External Interrupt Timing
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6-21
General-Purpose Output Timing
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6-22
GPIO Input Qualifier – Example Diagram for QUALPRD = 1
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Copyright © 2009–2010, Texas Instruments Incorporated
List of Figures
5