Intel N450 AU80610004653AA User Manual

60

Datasheet

While in the C2 state, the processor core will process bus snoops. The processor core 
will enter a snoopable sub-state described in the following section (and shown in Figure 
31), to process the snoop and return to the C2 state.

When STPCLK# pin is asserted, each thread of the processor cores enter the Stop-
Grant state within 1384 bus clocks after the response phase of the processor-issued 
Stop-Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted, the 
core returns to its previous low-power state.

RSTIN# causes the processor core to immediately initialize itself, but the processor 
core will stay in Stop-Grant state. When RSTIN# is asserted by the system, the 
STPCLK#, DPSLP#, and DPRSTP# pins must be de-asserted prior to RSTIN# de-
assertion.

While in Stop-Grant state, the processor core will service snoops and latch interrupts 
delivered on the internal bus. The processor core will latch SMI#, INIT# and LINT[1:0] 
interrupts and will service only one of each upon return to the Normal state.

The PBE# (FERR#) signal may be driven when the processor core is in Stop-Grant 
state. PBE# will be asserted if there is any pending interrupt or Monitor event latched 
within the processor core. Pending interrupts that are blocked by the EFLAGS. IF bit 
being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system 
logic that the entire processor core should return to the Normal state.

A transition to the Stop-Grant Snoop state occurs when the processor core detects a 
snoop on the internal bus. 

The processor core responds to snoop or interrupt transactions on the internal bus 
while in Stop-Grant state by entering the Stop-Grant Snoop state. The processor core 
will stay in this state until the snoop on the internal bus has been serviced (whether by 
the processor core or another agent on the internal bus) or the interrupt has been 
latched. The processor core returns to the Stop-Grant state once the snoop has been 
serviced or the interrupt has been latched.

The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep 
state. BCLK may be stopped during the Deep Sleep state for additional platform level 
power savings. Deep Sleep State is mapped into the Deeper Sleep State for this 
processor.

BCLK stop/restart timings on appropriate chipset-based platforms with the clock chip 
are as follows:

•

Deep Sleep entry: the system clock chip may stop/tri-state BCLK within 2 BCLKs 
of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.