Intel N450 AU80610004653AA User Manual

62

Datasheet

The transition to the lowest operating point or back to the original software requested 
point may not be instantaneous. Furthermore, upon very frequent transitions between 
active and idle states, the transitions may lag behind the idle state entry resulting in 
the processor either executing for a longer time at the lowest operating point or 
running idle at a high operating point. Observations and analyses show this behavior 
should not significantly impact total power savings or performance score while 
providing power benefits in most other cases.

Being used as DPRSLPVR is an alternate functionality for the PM_EXTTS1# signal. This 
implementation enables power savings by speeding up the C4 exit latency. To enable 
power savings, the PM_EXTTS1#/DPRSLPVR of the processor and the DPSLPVR signal 
of the chipset should be connected as shown in 

below. The DPRSLPVR signal 

of the chipset needs to be connected to the DPRSLPVR signal of the IMVP6 via a 
500ohm series isolation resistor. The pull-up on the PM_EXTTS1# signal should be 
removed in this particular implementation.

This implementation enables power-savings by increasing average C-state residency of
the processor (The probability of the CPU going into C4/C4E state increases if the exit 
latency is reduced).

With this implementation, PM_EXTTS1# cannot be used for thermal throttling of 
Memory. If this implementation is chosen, system designers shall need to ensure that 
the memory Auto-refresh rate programmed on their systems is the most appropriate 
for their thermal solution and choice of memory.

Intel strongly recommends the implementation described above, to enable greater 
power savings on the processor. For details of the recommended routing topologies and 
guidelines, please contact your Intel Field Representative.

Note: PM_EXTTS0# cannot be used in this manner.