Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  3   CPU  ARCHITECTURE 

R01UH0305EJ0200  Rev.2.00 

 

 

87  

Jul 04, 2013 

 

Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as 

a base address, and 8-bit immediate data or 16-bit immediate data as offset data.  The sum of these values is used 

to specify the target address. 

 

 

Identifier Description 

− 

[HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)

− 

word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) 

− 

word[BC] (only the space from F0000H to FFFFFH is specifiable) 

− 

ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) 

− 

ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) 

− 

ES:word[BC] (higher 4-bit addresses are specified by the ES register) 

FFFFFH

F0000H

SP

Target memory

Memory

Offset

Stack area

Specifies a 

stack area

Instruction code

<1>

<1>

byte

<2>

<2>

SP (stack pointer) <1> indicates the stack as the

target.

By indicating an offset from the address (top of the

stack) currently pointed to by the stack pointer,

“byte” <2> indicates the target memory (SP + byte).