Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  4   PORT  FUNCTIONS 
R01UH0305EJ0200  Rev.2.00 
 
 
102  
Jul 04, 2013 
4.2.11  Port 14 
Port 14 is an I/O port with an output latch.  Port 14 can be set to the input mode or output mode in 1-bit units using port 
mode register 14 (PM14).  When the P140, P141 pins are used as an input port, use of an on-chip pull-up resistor can be 
specified in 1-bit units by pull-up resistor option register 14 (PU14).   
This port can also be used for clock/buzzer output, and external interrupt request input, 
Reset signal generation sets P140, P141 to input mode. 
 
4.2.12  Port 15 
Port 15 is an I/O port with an output latch.  Port 15 can be set to the input mode or output mode in 1-bit units using port 
mode register 15 (PM15).   
This port can also be used for A/D converter analog input. 
To use P150/ANI8 to P154/ANI12 as digital input pins, set them in the digital I/O mode by using the A/D port 
configuration register (ADPC) and in the input mode by using the PM15 register.  Use these pins starting from the upper 
bit. 
To use 150/ANI8 to P154/ANI12 as digital output pins, set them in the digital I/O mode by using the A/D port 
configuration register (ADPC) and in the output mode by using the PM15 register.  Use these pins starting from the upper 
bit. 
To use 150/ANI8 to P154/ANI12 as analog input pins, set them in the analog input mode by using the A/D port 
configuration register (ADPC) and in the input mode by using the PM15 register.  Use these pins starting from the lower bit. 
 
Table 4-3.  Setting Functions of P150/ANI8 to P154/ANI12 Pins 
ADPC Register 
PM15 Register 
ADS Register 
P150/ANI8 to P154/ANI12 Pins 
Input mode 
− 
Digital input 
Digital I/O selection 
Output mode 
− 
Digital output 
Selects ANI. 
Analog input (to be converted) 
Input mode 
Does not select ANI. 
Analog input (not to be converted)
Selects ANI. 
Analog input selection 
Output mode 
Does not select ANI. 
Setting prohibited 
 
All P150/ANI8 to P154/ANI12 are set in the analog input mode when the reset signal is generated. 
 
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