Renesas rl78 User Manual

RL78/G1A

CHAPTER 5 CLOCK GENERATOR

R01UH0305EJ0200 Rev.2.00

169

Jul 04, 2013

Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers.

Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5)

(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)

Status Transition

SFR Register Setting

(A)

→ (B)

SFR registers do not have to be set (default status after reset release).

(2) CPU operating with high-speed system clock (C) after reset release (A)

(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)

(Setting sequence of SFR registers)

CMC Register

Note

CSC

CKC

Setting Flag of SFR Register

Status Transition

EXCLK OSCSEL AMPH

OSTS

MSTOP

OSTC Register

MCM0

(A)

→ (B) → (C)

(X1 clock: 1 MHz

≤ f

≤ 10 MHz)

0 1 0

Note 2

Must be

checked

(A)

→ (B) → (C)

(X1 clock: 10 MHz < f

≤ 20 MHz)

0 1 1

Note 2

Must be

checked

(A)

→ (B) → (C)

(external main clock)

1 1

Note 2

Must not be

checked

Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory

manipulation instruction after reset release.

2. Set the oscillation stabilization time as follows.

• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤

Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)

Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see

CHAPTER 29 ELECTRICAL SPECIFICATIONS (T

−40 to +85°C), CHAPTER 30 ELECTRICAL

SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T

−40 to + 105°C).

(3) CPU operating with subsystem clock (D) after reset release (A)

(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)

(Setting sequence of SFR registers)

CMC Register

Note

CSC

CKC

Setting Flag of SFR Register

Status Transition

EXCLKS OSCSELS AMPHS1 AMPHS0

XTSTOP

Waiting for

Oscillation

Stabilization

CSS

(A)

→ (B) → (D)

(XT1 clock)

0 1 0/1

0/1 0

Necessary

(A)

→ (B) → (D)

(external sub clock)

1 1

0 Necessary 1

Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation

instruction after reset release.

Remarks 1. ×: don’t care

2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15.