Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

223  

Jul 04, 2013 

The count clock (f

TCLK

) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes 

next rising f

MCK

.  The count clock (f

TCLK

) is delayed for 1 to 2 period of f

MCK

 from the input signal via the TImn pin 

(when a noise filter is used, the delay becomes 3 to 4 clock). 

Counting of timer count register mn (TCRmn) delayed by one period of f

CLK

 from rising edge of the count clock, 

because of synchronization with f

CLK

.  But, this is described as “counting at valid edge of input signal via the TImn 

pin”, as a matter of convenience.   

 

 

<1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input 

signal via the TImn pin. 

<2>  The rise of input signal via the TImn pin is sampled by f

MCK

. 

<3>  The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output. 

 

Remarks 1.   

: Rising edge of the count clock 

 

: Synchronization, increment/decrement of counter 

 

2.  f

CLK

: CPU/peripheral hardware clock 

 

 

f

MCK

: Operation clock of channel n 

 

3.  The waveform of the input signal via TImn pin of the input pulse interval measurement, the 

measurement of high/low width of input signal, and the delay counter, the one-shot pulse 

output are the same as that shown in Figure 6-22. 

 4.  m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), 

timer output pin (TOmn) : n = 0, 1, 3 to 7)) 

 

f

MCK

TSmn (write)

TEmn

TImn input

<1> 

<2>

Rising edge

detection signal (f

TCLK

)

Sampling wave

Edge detection

Edge detection 

<3>