Renesas rl78 User Manual
RL78/G1A
CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
237
Jul 04, 2013
6.6.4 Collective manipulation of TOmn bit
In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as
timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively.
Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond
to the relevant bits of the channel used to perform output (TOmn).
Figure 6-36. Example of TO0n Bit Collective Manipulation
Before writing
TO0 0 0 0 0 0 0 0 0
TO07
0
TO06
0
TO05
1
TO04
0
TO03
0
0 TO01
1
TO00
0
TOE0 0 0 0 0 0 0 0 0
TOE07
0
TOE06
0
TOE05
1
TOE04
0
TOE03
1
0 TOE01
1
TOE00
1
Data to be written
0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
After writing
TO0 0 0 0 0 0 0 0 0
TO07
1
TO06
1
TO05
1
TO04
0
TO03
0
0 TO01
1
TO00
0
Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored.
TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is
done to the TOmn bit, it is ignored and the output change by timer operation is normally done.
Figure 6-37. TO0n Pin Statuses by Collective Manipulation of TO0n Bit
TO07
TO06
TO05
TO04
TO03
TO01
TO00
Two or more TO0n output can
be changed simultaneously
be changed simultaneously
Output does not change
when value does not
change
when value does not
change
Before writing
Writing to the TO0n bit is
ignored when TOE0n
= 1
ignored when TOE0n
= 1
Writing to the TO0n bit
(Caution and Remark are given on the next page.)
O
O
O
×
×
×
×
×