Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  6   TIMER  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

240  

Jul 04, 2013 

When timer input pins are not used, the operating clock is not supplied to the noise filters.  When use of a timer input 

pin is specified, therefore, the system must wait for the time shown below until the channel operation enable trigger flag for 

the channel corresponding to the timer input pin is set. 

 

If bit 12 (CCSmn), bit 9 (STSmn1), or bit 8 (STSmn0) of timer mode register mn (TMRmn) is set when all of these 

bits are 0, wait for at least two cycles of the operating clock (f

MCK

), and then set the corresponding timer operation 

enable trigger flag of the timer channel start register (TSm). 

 

If bit 12 (CCSmn), bit 9 (STSmn1), or bit 8 (STSmn0) of timer mode register mn (TMRmn) is set when all of these 

bits are 0, wait for at least four cycles of the operating clock (f

MCK

), and then set the corresponding timer operation 

enable trigger flag of the timer channel start register (TSm).