Renesas rl78 User Manual

Page of 1004
 
RL78/G1A 
 
CHAPTER  6   TIMER  ARRAY  UNIT 
R01UH0305EJ0200  Rev.2.00 
 
 
283  
Jul 04, 2013 
6.9.3  Operation as multiple PWM output function 
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values 
can be output. 
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the 
following expressions. 
 
Pulse period = {Set value of TDRmn (master) + 1} 
× Count clock period 
Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} 
× 100 
Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} 
× 100 
 
Remark  Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn 
(master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is 
summarized into 100% output. 
 
Timer count register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods. 
The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM 
waveform from the TOmp pin.  The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of 
the master channel as a start trigger, and starts counting down.  When TCRmp = 0000H, TCRmp outputs INTTMmp and 
stops counting until the next start trigger (INTTMmn of the master channel) has been input.  The output level of TOmp 
becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp = 
0000H. 
In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in 
one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin.  The TCRmq register loads the 
value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down.  When 
TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the 
master channel) has been input.  The output level of TOmq becomes active one count clock after generation of INTTMmn 
from the master channel, and inactive when TCRmq = 0000H. 
When channel 0 is used as the master channel as above, up to six types of PWM signals can be output at the same 
time. 
 
Caution  To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the 
slave channel 1, write access is necessary at least twice.  Since the values of the TDRmn and TDRmp 
registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master 
channel, if rewriting is performed separately before and after generation of INTTMmn from the master 
channel, the TOmp pin cannot output the expected waveform.  To rewrite both the TDRmn register of 
the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately 
after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the 
slave channel 2). 
 
Remark  m: Unit number (m = 0), n: Channel number (n = 0, 2, 4) 
 
p: Slave channel number 1, q: Slave channel number 2 
 
n < p < q 
≤ 7 
 
However, timer output pin (TOmp, TOmq) : p = 1, 3 to 6, q = 3 to 7