Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  11   A/D  CONVERTER 

R01UH0305EJ0200  Rev.2.00 

 

 

382  

Jul 04, 2013 

 

<1>  In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the 

A/D conversion standby status. 

<2>  If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the 

four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel 

specification register (ADS).  The ADCS bit of the ADM0 register is automatically set to 1 according to the 

hardware trigger input.  A/D conversion is performed on the analog input channels in order, starting with that 

specified by scan 0. 

<3>  A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in 

the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end 

interrupt request signal (INTAD) is generated.  After A/D conversion of the four channels ends, the A/D 

conversion of the channel following the specified channel automatically starts. 

<4>  If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and 

conversion restarts at the first channel.  The partially converted data is discarded. 

<5>  When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D 

conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.  

The partially converted data is discarded. 

<6>  When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and 

conversion restarts at the first channel.  The partially converted data is discarded. 

<7>  When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system 

enters the hardware trigger standby status, and the A/D converter enters the stop status.  When ADCE = 0, 

inputting a hardware trigger is ignored and A/D conversion does not start. 

 

 

ADCE

ADCS

ADS

INTAD

ADCR,

ADCRH

A/D

conversion

status

ADCE is set to 1.

<1>

The trigger is not

acknowledged.

Stop status

Stop status

Data 1
(ANI0)

Data 1
(ANI0)

Data 2
(ANI1)

Data 2
(ANI1)

Data 3
(ANI2)

Data 3
(ANI2)

Data 4
(ANI3)

Data 7
(ANI0)

Data 8
(ANI1)

Data 14

(ANI5)

Data 21

(ANI5)

Data 21

(ANI5)

Data 14

(ANI5)

Data 13

(ANI4)

Data 13

(ANI4)

Data 20

(ANI4)

Data 24

(ANI4)

Data 20

(ANI4)

Data 17

(ANI4)

Data 17

(ANI4)

Data 18

(ANI5)

Data 18

(ANI5)

Data 8
(ANI1)

Data 9
(ANI2)

Data 9
(ANI2)

Data 10

(ANI3)

Data 11

(ANI0)

Data 10

(ANI3)

Data 16

(ANI7)

Data 23

(ANI7)

Data 23

(ANI7)

Data 16

(ANI7)

Data 15

(ANI6)

Data 22

(ANI6)

Data 22

(ANI6)

Data 15

(ANI6)

Data 4
(ANI3)

Data 11

(ANI0)

Data 5
(ANI0)

Data 6
(ANI1)

Data 12

(ANI1)

Data 19

(ANI6)

Conversion is 
interrupted and restarts.

Conversion is 
interrupted and restarts.

Conversion is

interrupted.

Conversion is 
interrupted and restarts.

A/D conversion 

ends  and the next 

conversion starts.

<3>

<3>

<3>

<3>

ADS is rewritten during 
A/D conversion operation.

<5>

The interrupt is generated four times.

The interrupt is generated four times.

The interrupt is generated four times.

The interrupt is generated four times.

Trigger 

standby status

Hardware

trigger

A hardware trigger 
is generated.

<2>

A hardware trigger is 
generated during A/D 
conversion operation.

<4>

ADCS is overwritten 

with 1 during A/D 

conversion operation.

<6>

ADCS is cleared 

to 0 during A/D 

conversion operation.

Trigger 
standby

status

<7>

The trigger
is not
acknowledged.

Data 5
(ANI0)

ANI0 to ANI3

ANI4 to ANI7

Data 7
(ANI0)