Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  11   A/D  CONVERTER 

R01UH0305EJ0200  Rev.2.00 

 

 

385  

Jul 04, 2013 

11.7.1  Setting up software trigger mode 
 

 

 

Start of setup 

PER0 register setting 

ADPC and PMCx register settings 

PM register setting 

The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. 

The ports are set to analog input. 

ANI0 to ANI12 pins: Set using the ADPC register 

ANI16 to ANI30 pins: Set using the PMCx register 

The ports are set to the input mode. 

• ADM0 register 

FR2 to FR0, LV1, and LV0 bits:  These are used to specify the A/D conversion time.
ADMD bit: 

Select mode/scan mode 

• ADM1 register 

ADTMD1 and ADTMD0 bits:  These are used to specify the software trigger mode.
ADSCM bit:  Sequential conversion mode/one-shot conversion mode 

• ADM2 register 

ADREFP1, ADREFP0, and ADREFM bits:  These are used to select the reference 

voltage. 

ADRCK bit:  This is used to select the range for the A/D conversion result 

comparison value generated by the interrupt signal from AREA1, 
AREA3, and AREA2. 

ADTYP bit:  8-bit/12-bit resolution 

• ADUL/ADLL register 
  These are used to specify the upper limit and lower limit A/D conversion result 

comparison values. 

• ADS register 
  ADS4 to ADS0 bits: These are used to select the analog input channels. 

ADCE bit setting 

The ADCE bit of the ADM0 register is set (1), and the system enters the A/D 

conversion standby status.  

Reference voltage stabilization 

wait time count B 

If a high-accuracy channel is selected as the analog input channel:  B = 0.5 

μs 

If a standard channel is selected as the analog input channel:  

B = 2 

μs 

Start of A/D conversion 

End of A/D conversion 

The A/D conversion operations are performed. 

The A/D conversion end interrupt request signal (INTAD) is generated.

 

Storage of conversion results in 

the ADCR and ADCRH registers 

The conversion results are stored in the ADCR and ADCRH registers. 

ADCS bit setting 

After completion of the reference voltage stabilization wait time count B, the ADCS bit 

of the ADM0 register is set (1), and A/D conversion starts. 

Reference voltage stabilization 

wait time count A 

The reference voltage stabilization wait time count A is required when the value of the 
ADREFP1 and ADREFP0 bits is changed. 
If change the ADREFP1 and ADREFP0 = 1, 0: 

A = 10 

μs 

If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1:  A = 1 

μs 

 

• ADM0 register setting 
• ADM1 register setting 
• ADM2 register setting 
•  ADUL/ADLL register setting 
• ADS register setting 
  (The order of the settings is 

irrelevant.) 

 

 

Note  Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no A/D conversion 

end interrupt request signal (INTAD) being generated.  In this case, the results are not stored in the ADCR, 

ADCRH registers. 

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