Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

 

ACKD0 

Detection of acknowledge (ACK) 

0 

Acknowledge was not detected. 

1 

Acknowledge was detected. 

Condition for clearing (ACKD0 = 0) 

Condition for setting (ACKD0 = 1) 

• When a stop condition is detected 

• After the SDAA0 line is set to low level at the rising 

edge of SCLA0 line’s ninth clock 

• At the rising edge of the next byte’s first clock 
• Cleared by LREL0 = 1 (exit from communications) 
• When the IICE0 bit changes from 1 to 0 (operation 

stop) 

• Reset 

STD0 

Detection of start condition 

0 

Start condition was not detected. 

1 

Start condition was detected.  This indicates that the address transfer period is in effect. 

Condition for clearing (STD0 = 0) 

Condition for setting (STD0 = 1) 

• When a stop condition is detected 

• When a start condition is detected 

• At the rising edge of the next byte’s first clock 

following address transfer  

• Cleared by LREL0 = 1 (exit from communications) 
• When the IICE0 bit changes from 1 to 0 (operation 

stop) 

• Reset 

SPD0 

Detection of stop condition 

0 

Stop condition was not detected. 

1 

Stop condition was detected.  The master device’s communication is terminated and the bus is 

released. 

Condition for clearing (SPD0 = 0) 

Condition for setting (SPD0 = 1) 

• At the rising edge of the address transfer byte’s first 

clock following setting of this bit and detection of a 

start condition   

• When a stop condition is detected 

• When the WUP0 bit changes from 1 to 0  
• When the IICE0 bit changes from 1 to 0 (operation 

stop) 

• Reset 

Remark   LREL0:   Bit 6 of IICA control register 00 (IICCTL00) 

 

IICE0:   Bit 7 of IICA control register 00 (IICCTL00) 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013