Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

 

To start master device communications when not currently using a bus, a communication reservation can be made 

to enable transmission of a start condition when the bus is released.  There are two modes under which the bus is 

not used. 

 

•  When arbitration results in neither master nor slave operation 

•  When an extension code is received and slave operation is disabled (ACK is not returned and the bus was 

released by setting bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 and saving communication). 

 

If bit 1 (STT0) of the IICCTL00 register is set to 1 while the bus is not used (after a stop condition is detected), a 

start condition is automatically generated and wait state is set.  

If an address is written to the IICA shift register 0 (IICA0) after bit 4 (SPIE0) of the IICCTL00 register was set to 1, 

and it was detected by generation of an interrupt request signal (INTIICA0) that the bus was released (detection of 

the stop condition), then the device automatically starts communication as the master.  Data written to the IICA0 

register before the stop condition is detected is invalid. 

When the STT0 bit has been set to 1, the operation mode (as start condition or as communication reservation) is 

determined according to the bus status. 

 

•  If the bus has been released ........................................ a start condition is generated 

•  If the bus has not been released (standby mode)......... communication reservation 

 

Check whether the communication reservation operates or not by using the MSTS0 bit (bit 7 of the IICA status 

register 0 (IICS0)) after the STT0 bit is set to 1 and the wait time elapses. 

Use software to secure the wait time calculated by the following expression. 

 

Wait time from setting STT0 = 1 to checking the MSTS0 flag (number of clocks of f

MCK

): 

(IICWL0 setting value + IICWH0 setting value + 4) + t

F

 

× 2 × f

MCK

 [clocks]

 

 

Remark  IICWL0:   IICA low-level width setting register 0 

 

IICWH0:   IICA high-level width setting register 0 

 

t

F

:  

SDAA0 and SCLA0 signal falling times 

 

f

MCK

: 

IICA operation clock frequency 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013