Renesas rl78 User Manual
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
Figure 13-32. Example of Master to Slave Communication
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
(1) Start condition ~ address ~ data
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
W
ACK
<2>
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
Master side
Bus line
Slave side
Slave address
L
L
H
L
H
H
H
L
AD5
AD4
AD3
AD2
AD1
AD0
WTIM0
(8 or 9 clock wait)
Note 1
Start condition
D
1
7
AD6
Note 2
Note 3
<5>
<1>
<4>
<3>
<6>
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a master
device.
2.
Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is
at least 4.0
μ
s when specifying standard mode and at least 0.6
μ
s when specifying fast mode.
3. For releasing wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.
R01UH0305EJ0200 Rev.2.00
638
Jul 04, 2013