Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  13   SERIAL  INTERFACE  IICA 

The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 13-32 are explained below. 

 

<3>  In the slave device if the address received matches the address (SVA0 value) of a slave device

, that 

slave device sends an ACK by hardware to the master device.  The ACK is detected by the master device 

(ACKD0 = 1) at the rising edge of the 9th clock. 

<4>  The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th 

clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 = 

0) and issues an interrupt (INTIICA0: address match)

. 

<5>  The master device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait 

status that it set by the master device. 

<6>  If the slave device releases the wait status (WREL0 = 1), the master device starts transferring data to the 

slave device. 

<7>  After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the 

master device.  The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. 

<8>  The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and 

both the master device and slave device issue an interrupt (INTIICA0: end of transfer). 

<9>  The master device writes the data to transmit to the IICA0 register and releases the wait status that it set by 

the master device. 

<10> The slave device reads the received data and releases the wait status (WREL0 = 1).  The master device 

then starts transferring data to the slave device. 

 

Note  If the transmitted address does not match the address of the slave device, the slave device does not return 

an ACK to the master device (NACK: SDAA0 = 1).  The slave device also does not issue the INTIICA0 

interrupt (address match) and does not set a wait status.  The master device, however, issues the INTIICA0 

interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. 

 

Remark  <1> to <15> in Figure 13-32 represent the entire procedure for communicating data using the I

2

C bus.   

Figure 13-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 13-32 

(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 13-32 (3) Data ~ data ~ 

stop condition shows the processing from <7> to <15>. 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013