Renesas rl78 User Manual
RL78/G1A
CHAPTER 15 DMA CONTROLLER
15.5.2 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 = 0001B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register (ADCR) to 512 bytes of
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 = 0001B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register (ADCR) to 512 bytes of
FFCE0H to FFEDFH of RAM.
Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1)
R01UH0305EJ0200 Rev.2.00
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Jul 04, 2013