Renesas rl78 User Manual

RL78/G1A

CHAPTER 21 VOLTAGE DETECTOR

Notes 1. The LVIMK flag is set to “1” by reset signal generation.

2. After an interrupt is generated, perform the processing according to Figure 21-7 Processing Procedure

After an Interrupt Is Generated.

3. After a reset is released, perform the processing according to Figure 21-8 Initial Setting of Interrupt and

Reset Mode.

Remark V

POR

: POR power supply rise detection voltage

PDR

: POR power supply fall detection voltage

Figure 21-7. Processing Procedure After an Interrupt Is Generated

<R>

INTLVI generated

LVISEN = 1

Set the LVISEN bit to 1 to mask voltage detection

(LVIOMSK = 1).

LVISEN = 0

Set the LVISEN bit to 0 to enable voltage

detection.

Yes

LVD reset generated

When an internal reset by voltage detector (LVD)
is not generated, a condition of V

becomes V

≥

LVDH

Set the LVILV bit to 0 to set the high-voltage

detection level (V

LVDH

LVILV = 0

LVISEN = 1

Set the LVISEN bit to 1 to mask voltage detection

(LVIOMSK = 1)

LVISEN = 0

Set the LVISEN bit to 0 to enable voltage

detection.

Set the LVIMD bit to 0 to set interrupt mode.

LVIMD = 0

Internal reset by LVD

is generated

Yes

LVIOMSK = 0

Normal operation

Save processing

Perform required save processing.

R01UH0305EJ0200 Rev.2.00

768

Jul 04, 2013