Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  23   REGULATOR 

 

 

 

The RL78/G1A contains a circuit for operating the device with a constant voltage.  At this time, in order to stabilize the 

regulator output voltage, connect the REGC pin to V

SS

 via a capacitor (0.47 to 1 

μ

F).  Also, use a capacitor with good 

characteristics, since it is used to stabilize internal voltage. 

 

REGC

V

SS

 

 

 

The regulator output voltage, see Table 23-1. 

 

Mode Output 

Voltage 

Condition 

LV (Low voltage main) mode 

LS (Low-speed main) mode 

1.8 V 

− 

In STOP mode  

When both the high-speed system clock (f

MX

) and the high-speed on-chip 

oscillator clock (f

IH

) are stopped during CPU operation with the subsystem clock 

(f

SUB

)  

1.8 V 

When both the high-speed system clock (f

MX

) and the high-speed on-chip 

oscillator clock (f

IH

) are stopped during the HALT mode when the CPU operation 

with the subsystem clock (f

SUB

) has been set  

HS (High-speed main) mode 

2.1 V 

Other than above  (include during OCD mode)

 

Note  When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output 

voltage is kept at 2.1 V (not decline to 1.8 V). 

 

R01UH0305EJ0200  Rev.2.00 

 

 

791  

Jul 04, 2013