Renesas rl78 User Manual
RL78/G1A
CHAPTER 28 INSTRUCTION SET
R01UH0305EJ0200 Rev.2.00
841
Jul 04, 2013
Table 28-5. Operation List (9/17)
Notes 1. Number of CPU clocks (f
CLK
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2.
Number of CPU clocks (f
CLK
) when the code flash memory is accessed, or when the data flash memory is
accessed by an 8-bit instruction.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group
Mnemonic Operands Bytes
Note 1
Note 2
Clocks
Z AC CY
A, #byte
2
1
−
A
← A∨byte ×
saddr, #byte
3
2
−
(saddr)
← (saddr)∨byte ×
A, r
Note 3
2
1
−
A
← A∨r ×
r, A
2
1
−
r
← r∨A ×
A, !addr16
3
1
4
A
← A∨(addr16) ×
A, ES:!addr16
4
2
5
A
← A∨(ES:addr16) ×
A, saddr
2
1
−
A
← A∨(saddr) ×
A, [HL]
1
1
4
A
← A∨(H) ×
A, ES:[HL]
2
2
5
A
← A∨(ES:HL) ×
A, [HL+byte]
2
1
4
A
← A∨(HL+byte) ×
A, ES:[HL+byte]
3
2
5
A
← A∨((ES:HL)+byte) ×
A, [HL+B]
2
1
4
A
← A∨(HL+B) ×
A, ES:[HL+B]
3
2
5
A
← A∨((ES:HL)+B) ×
A, [HL+C]
2
1
4
A
← A∨(HL+C) ×
OR
A, ES:[HL+C]
3
2
5
A
← A∨((ES:HL)+C) ×
A, #byte
2
1
−
A
← A∨byte ×
saddr, #byte
3
2
−
(saddr)
← (saddr)∨byte ×
A, r
Note 3
2
1
−
A
← A∨r ×
r, A
2
1
−
r
← r∨A ×
A, !addr16
3
1
4
A
← A∨(addr16) ×
A, ES:!addr16
4
2
5
A
← A∨(ES:addr16) ×
A, saddr
2
1
−
A
← A∨(saddr) ×
A, [HL]
1
1
4
A
← A∨(HL) ×
A, ES:[HL]
2
2
5
A
← A∨(ES:HL) ×
A, [HL+byte]
2
1
4
A
← A∨(HL+byte) ×
A, ES:[HL+byte]
3
2
5
A
← A∨((ES:HL)+byte) ×
A, [HL+B]
2
1
4
A
← A∨(HL+B) ×
A, ES:[HL+B]
3
2
5
A
← A∨((ES:HL)+B) ×
A, [HL+C]
2
1
4
A
← A∨(HL+C)
×
8-bit
operation
XOR
A, ES:[HL+C]
3
2
5
A
← A∨((ES:HL)+C) ×
<R>