Renesas rl78 User Manual
4.4.4
Handling different potential (1.8 V or 2.5 V) by using EV
DD
≤ V
DD
............................................... 116
4.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers ................................................ 116
4.5
Register Settings When Using Alternate Function.............................................................. 118
4.5.1
Basic concept when using alternate function .............................................................................. 118
4.5.2
Register settings for alternate function whose output function is not used ................................. 119
4.5.3
Register setting examples for used port and alternate functions ................................................ 120
4.6
Cautions When Using Port Function..................................................................................... 137
4.6.1
Cautions on 1-bit manipulation instruction for port register n (Pn) .............................................. 137
4.6.2
Notes on specifying the pin settings ........................................................................................... 138
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 139
5.1 Functions
of
Clock
Generator................................................................................................ 139
5.2
Configuration of Clock Generator ......................................................................................... 141
5.3
Registers Controlling Clock Generator................................................................................. 143
5.3.1
Clock operation mode control register (CMC)............................................................................. 143
5.3.2
System clock control register (CKC) ........................................................................................... 146
5.3.3
Clock operation status control register (CSC)............................................................................. 147
5.3.4
Oscillation stabilization time counter status register (OSTC) ...................................................... 148
5.3.5
Oscillation stabilization time select register (OSTS) ................................................................... 150
5.3.6 Peripheral
enable register 0 (PER0) ........................................................................................... 152
5.3.7
Subsystem clock supply mode control register (OSMC) ............................................................. 155
5.3.8
High-speed on-chip oscillator frequency select register (HOCODIV).......................................... 156
5.3.9
High-speed on-chip oscillator trimming register (HIOTRM)......................................................... 157
5.4 System
Clock
Oscillator ......................................................................................................... 158
5.4.1 X1
oscillator ................................................................................................................................ 158
5.4.2 XT1
oscillator .............................................................................................................................. 158
5.4.3 High-speed
on-chip oscillator...................................................................................................... 162
5.4.4 Low-speed
on-chip oscillator ...................................................................................................... 162
5.5
Clock Generator Operation .................................................................................................... 163
5.6 Controlling
Clock .................................................................................................................... 165
5.6.1
Example of setting high-speed on-chip oscillator........................................................................ 165
5.6.2 Example
of
setting
X1 oscillation clock ....................................................................................... 166
5.6.3 Example
of
setting
XT1 oscillation clock ..................................................................................... 167
5.6.4
CPU clock status transition diagram ........................................................................................... 168
5.6.5 Condition
before changing CPU clock and processing after changing CPU clock...................... 174
5.6.6
Time required for switchover of CPU clock and system clock..................................................... 176
5.6.7
Conditions before clock oscillation is stopped............................................................................. 177
5.7
Resonator and Oscillator Constants..................................................................................... 178
CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 182
6.1
Functions of Timer Array Unit ............................................................................................... 184
6.1.1 Independent
channel operation function ..................................................................................... 184
6.1.2 Simultaneous
channel operation function ................................................................................... 185
6.1.3
8-bit timer operation function (channels 1 and 3 only) ................................................................ 186
6.1.4
LIN-bus supporting function (channel 7 of unit 0 only) ................................................................ 187
6.2
Configuration of Timer Array Unit ......................................................................................... 188
Index-3