Renesas rl78 User Manual
RL78/G1A
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T
A
=
−40 to +105°C)
R01UH0305EJ0200 Rev.2.00
926
Jul 04, 2013
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(T
A
=
−40 to +105°C, 2.4 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time
becomes “from SCKp
↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes
“from SCKp
↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin
by using port input mode register g (PIMg) and port output mode register g (POMg).
Remark p: CSI number (p = 00, 01, 10, 11, 20, 21), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM numbers (g = 0, 1)
Parameter Symbol Conditions
MIN.
TYP.
MAX.
Unit
2.7 V
≤ EV
DD0
≤ 3.6 V
t
KCY1
≥ 4/f
CLK
250
ns
SCKp cycle time
t
KCY1
2.4 V
≤ EV
DD0
≤ 3.6 V
t
KCY1
≥ 4/f
CLK
500
ns
2.7 V
≤ EV
DD0
≤ 3.6 V
t
KCY1
/2
− 36
ns
SCKp high-/low-level width
t
KH1
,
t
KL1
2.4 V
≤ EV
DD0
≤ 3.6 V
t
KCY1
/2
− 76
ns
2.7 V
≤ EV
DD0
≤ 3.6 V
66
ns
SIp setup time (to SCKp
↑)
Note 1
t
SIK1
2.4 V
≤ EV
DD0
≤ 3.6 V
113
ns
SIp hold time (from SCKp
↑)
Note 1
t
KSI1
38
ns
Delay time from SCKp
↓ to
SOp output
Note 2
t
KSO1
C = 30 p
Note 3
50
ns