Intel N475 AU80610006240AA User Manual
Product codes
AU80610006240AA
Datasheet
57
Power Management
NOTES:
1.
1.
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, SMI# or APIC interrupt.
2.
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
3.
STPCLK# assertion and de-assertion have no effect if a thread is in C2 state.
Figure 5-7. Thread C-state
C 2
†
C 0
Stop
G rant
Core state
break
P_LVL2 or
M W AIT(C2)
C1/
M W A IT
Core state
break
M W AIT(C 1)
C 1/A uto
H alt
H alt break
H LT instruction
C 4
†
C ore State
break
P_LVL4 or
M W AIT(C 4)
STPCLK #
de-asserted
STPCLK#
asserted
STPC LK#
de-asserted
STPCLK #
asserted
STPCLK#
de-asserted
STPCLK#
asserted
Figure 5-8. Processor Core Low-power States
Stop Grant
Snoop
Normal
Stop
Grant
Deep
Sleep
STPCLK# asserted
Snoop
serviced
Snoop
occurs
occurs
Deeper
Sleep
DPSLP# asserted
DPSLP# de-asserted
DPRSTP# de-asserted
DPRSTP# asserted
STPCLK# de-asserted