Intel N475 AU80610006240AA User Manual

Product codes

AU80610006240AA

Power Management

Datasheet

NOTES:
1.

AutoHALT or MWAIT/C1

To enter a package state, both threads must be in a common low power state. If the
threads are not in a common low power state, the package state will resolve to the highest
power C state.

5.2.4

Thread C-states Description

5.2.4.1

Thread C0 State

This is the normal operating state for threads in the processor core.

5.2.4.2

Thread C1/AutoHALT Powerdown State

C1/AutoHALT is a low-power state entered when one thread executes the HALT
instruction while the other is in the TC1 or greater thread state. The processor core will
transition to the C0 state upon occurrence of SMI#, INIT#, LINT00/LINT10 (NMI,
INTR), or internal bus interrupt messages. RSTINB will cause the processor core to
immediately initialize itself.

A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT power down state. See the Intel

64 and IA-32 Architectures

Software Developer’s Manuals, Volume 3A/3B: System Programmer’s Guide for more
information.

The system can generate STPCLK# while the processor core is in the AutoHALT power
down state. When the system de-asserts the STPCLK# interrupt, the processor core
will return to the HALT state.

While in AutoHalt power down state, the processor core will process bus snoops. The
processor core will enter an internal snoopable sub-state to process the snoop and then
return to the AutoHALT power down state.

Table 5-42. Coordination of Thread Low-power States at the Package/Core Level

Processor

Core

C-State

Thread 1

Thread 0