Intel N475 AU80610006240AA User Manual
Product codes
AU80610006240AA
Datasheet
59
Power Management
5.2.4.3
Thread C1/MWAIT Power-down State
C1/MWAIT is a low-power state entered when one thread executes the MWAIT (C1)
instruction while the other thread is in the TC1 or greater thread state. processor core
behavior in the MWAIT state is identical to the AutoHALT state except that Monitor
events can cause the processor core to return to the C0 state. See the Intel
instruction while the other thread is in the TC1 or greater thread state. processor core
behavior in the MWAIT state is identical to the AutoHALT state except that Monitor
events can cause the processor core to return to the C0 state. See the Intel
®
64 and
IA-32 Architectures Software Developer’s Manuals, Volume 2A: Instruction Set
Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.
Reference, A-M and Volume 2B: Instruction Set Reference, N-Z, for more information.
5.2.4.4
Thread C2 State
Individual threads of the dual-threaded processor can enter the C2 state by initiating a
P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not
issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also
asserted.
P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not
issue a Stop-Grant Acknowledge special bus cycle unless the STPCLK# pin is also
asserted.
While in the C2 state, the processor will process bus snoops and snoops from the other
thread. The processor thread will enter a snoopable sub-state to process the snoop and
then return to the C2 state.
thread. The processor thread will enter a snoopable sub-state to process the snoop and
then return to the C2 state.
5.2.4.5
Thread C4 State
Individual threads of the processor can enter the C4 state by initiating a P_LVL4 I/O
read to the P_BLK or an MWAIT(C4) instruction. If both processor threads are in C4,
the central power management logic will request that the entire processor enter the
Deeper Sleep package low-power state.
read to the P_BLK or an MWAIT(C4) instruction. If both processor threads are in C4,
the central power management logic will request that the entire processor enter the
Deeper Sleep package low-power state.
To enable the package level Intel Enhanced Deeper Sleep state, Dynamic Cache Sizing
and Intel Enhanced Deeper Sleep state fields must be configured in the
PMG_CST_CONFIG_CONTROL MSR.
and Intel Enhanced Deeper Sleep state fields must be configured in the
PMG_CST_CONFIG_CONTROL MSR.
5.2.5
Processor Core/Package C-states Description
The following state descriptions assume that both threads are in a common low power
state. For cases when only one thread is in a low power state, no change in Core/
Package power state will occur (see
state. For cases when only one thread is in a low power state, no change in Core/
Package power state will occur (see
).
5.2.5.1
Normal State (C0, C1)
This is the normal operating state for the processor core. The processor core remains in
the Normal state when the processor core is in the C0, C1/AutoHALT, or C1/MWAIT
state. C0 is the active execution state.
the Normal state when the processor core is in the C0, C1/AutoHALT, or C1/MWAIT
state. C0 is the active execution state.
5.2.5.2
C2 State
Individual threads of the dual-threaded processor core can enter TC2 state by initiating
a P_LVL2 I/O read to the P_BLK or an MWAIT (C2) instruction. Once both threads have
C2 as a common state, the processor core will transition to the C2 state; however, the
processor core will not issue a Stop-Grant Acknowledge special bus cycle unless the
STPCLK# pin is also asserted by the chipset.
a P_LVL2 I/O read to the P_BLK or an MWAIT (C2) instruction. Once both threads have
C2 as a common state, the processor core will transition to the C2 state; however, the
processor core will not issue a Stop-Grant Acknowledge special bus cycle unless the
STPCLK# pin is also asserted by the chipset.