Motorola TMS320C6711D User Manual
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
63
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electrical characteristics over recommended ranges of supply voltage and operating case
temperature
temperature
†
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level output
voltage
All signals except CLKS1 and
DR1
DR1
DVDD
= MIN, IOH = MAX
2.4
V
VOL
Low-level output
voltage
All signals except CLKS1 and
DR1
DR1
DVDD
= MIN, IOL = MAX
0.4
V
VOL
voltage
CLKS1 and DR1
DVDD
= MIN, IOL = MAX
0.4
V
II
Input current
All signals except CLKS1 and
DR1
VI
= VSS to DVDD
±
170
uA
II
Input current
CLKS1 and DR1
VI
= VSS to DVDD
±
10
uA
IOZ
Off-state output
current
All signals except CLKS1 and
DR1
VO
= DVDD or 0 V
±
170
uA
IOZ
current
CLKS1 and DR1
VO
= DVDD or 0 V
±
10
uA
GDP, CVDD
= 1.4-V,
CPU clock = 250 MHz
810
IDD2V Core supply current‡
GDP/ZDP, CVDD =
1.26-V, CPU clock =
200 MHz
1.26-V, CPU clock =
200 MHz
560
mA
GDPA/ZDPA, CVDD
=
1.26-V, CPU clock =
167 MHz
167 MHz
475
IDD3V I/O supply current‡
DVDD
= 3.3-V, EMIF
speed = 100 MHz
75
mA
Ci
Input capacitance
7
pF
Co
Output capacitance
7
pF
† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡ For this device, these currents were measured with average activity (50% high/50% low power) at 25
‡ For this device, these currents were measured with average activity (50% high/50% low power) at 25
°
C case temperature and 100-MHz EMIF.
This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity
operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power
Consumption Summary application report (literature number SPRA889A).
Consumption Summary application report (literature number SPRA889A).