Intel E7520 User Manual
Dual-Core Intel
®
Xeon
®
processor LV with Intel
®
E7520 Chipset and Intel
®
6300ESB ICH
April 2007
User’s Manual
Order Number: 311274-009
31
Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH
3.3.10
Clock Generation
The CRB uses one CK409B Clock Synthesizer to generate the host differential pair
clocks and the 100MHz differential clock to the DB800. The DB800 then generates the
100 MHz differential pair clock for the PCI Express devices.
shows the CRB
clock configuration.
Figure 16.
Power Distribution Block Diagram
VRM
11
VCCP
0
0
.
8375
-
1
.
6000
V
50
A
VCCP
1
.
05
V
6
.
0
A
VCCP
1
0
.
8375
-
1
.
6000
V
50
A
DDR
1
.
8
V
50
A
3
.
3
VSTBY
3
.
0
A
1
.
5
V
13
A
3
.
3
AUX
1
.
7
A
1
.
8
VDDRSB
3
A
DIMMS
DDR
S
3
Switch
S
3
_
CNTRL
1
.
5
VSTBY
0
.
8
A
450
W ATX
5
.
0
VSTBY
2
.
5
A
-
12
V
1
A
3
.
3
V
28
A
5
.
0
V
50
A
12
V
18
A
-
5
.
0
V
0
.
5
A