Fujitsu FR81S User Manual
CHAPTER 25: 16-BIT OUTPUT COMPARE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
5.3. Notes on Using 16-bit Output Compare
The notes on using 16-bit output compare is shown.
⋅
Compare stop section in the compare operation
The compare operation is stopped for one count cycle just after a compare value is written to the
compare register as shown below.
N-2
N-1
N
N+1
N+2
N+3
X
N
Writing to compare register
Compare
Timing
Compare stop interval
In this case, a match signal
is not generated.
N-2
N-1
N
N+1
N+2
N+3
X
N
Count value of free-run timer
Compare register value
⋅
If the settings are CMOD = 1 and OCCP0 = OCCP1, OCCP2 = OCCP3 and OCCP4 = OCCP5, the
port is inverted only once when a compare match occurs.
⋅
Be sure to stop the compare operation before specifying the output level of the output compare output.
⋅
Stopping the free-run timer stops the compare operation because the output compare is in
synchronization with the free-run timer.
⋅
An interrupt operation occurs independently for each of OCU0 to OCU5 when the compare mode bit
CMOD is set to 1.
⋅
When the free-run timer is used as compare data for the output compare, the free-run timer clock
frequency (TCCSL.CLK[3:0]) cannot be set to "0000
B
".
Read-modify-write
The interrupt request flag bits (IOP0), (IOP1), (IOP2), (IOP3), (IOP4) and (IOP5) are "1" when read using a
read-modify-write instruction.
Notes on interrupts
When you set the interrupt flag bits (IOP1/IOP0) of the compare control register (OCS) to "1", then enable
the interrupt request (set the interrupt request enable bits (IOE1/IOE0) of the OCS to "1"), the controller
cannot return from the interrupt processing. Be sure to clear the interrupt flag bits (IOP1/IOP0).
MB91520 Series
MN705-00010-1v0-E
990