Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
6. Operation and Setting Procedure Examples
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
24
Figure 6-2 Clear Event Occurrence Timing
Reload Event
The up/down counter value is reloaded in one of the following events.
· The CTUT bit of the counter control register (CCR) is written to "1".
· The reload function is activated to reload the value:
· The reload function is activated to reload the value:
The timing the up/down counter value is reloaded depends on the up/down counter operating status as
follows.
follows.
· If a reload event occurs during counting:
The value will be reloaded in synchronization with the count clock.
· If a reload event occurs except during counting:
The value will be reloaded when a reload event occurs.
Notes:
· During counting, do not write "1" to the CTUT bit of the counter control register (CCR).
· If a reload event and a clear event occur at the same time, the clear event takes precedence.
· If a reload event and a clear event occur at the same time, the clear event takes precedence.
UDCR
Clear event
Count clock
UDCR : Up/down count register
Disable
0065
H
0066
H
0000
H
Count enable
Enable
MB91520 Series
MN705-00010-1v0-E
1031