Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
6. Operation and Setting Procedure Examples
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
25
6.1. Operation in Timer Mode
This section explains the operation in timer mode.
Overview
In this mode, the up/down counter counts down from the value set in the reload compare register (RCR).
The frequency of the peripheral clock (PCLK) is divided by the prescaler to ensure that the result can be
used as the count clock.
The frequency of the peripheral clock (PCLK) is divided by the prescaler to ensure that the result can be
used as the count clock.
It is also possible to use the reload function in order to reload the value of the reload compare register
(RCR) when the counter underflows, so that counting-down can be restarted from the reloaded value.
(RCR) when the counter underflows, so that counting-down can be restarted from the reloaded value.
Counting
Normal operation
1. The reload/compare value is set in the reload compare register (RCR).
2. When "1" is written to the CTUT bit of the counter control register (CCR), the set value is transferred
2. When "1" is written to the CTUT bit of the counter control register (CCR), the set value is transferred
to the up/down count register (UDCR).
3. When "1" is written to the CSTR bit of the counter status register (CSR) to enable up/down counter
operation, the counter begins to count down from the value set in the reload compare register (RCR).
When the counter underflows, the UDFF bit of the counter status register (CSR) changes to "1". At this
time, an underflow interrupt request occurs if the UDIE bit of the counter status register is set to "1".
time, an underflow interrupt request occurs if the UDIE bit of the counter status register is set to "1".
If the CGSC bit of the counter control register (CCR) is set to make the ZIN pin work for the gate function
(CGSC=1), the counter will only count while the effective level specified by the CGE1 and CGE0 bits is
entered from the ZIN pin.
(CGSC=1), the counter will only count while the effective level specified by the CGE1 and CGE0 bits is
entered from the ZIN pin.
For information on effective level setting, see "4.3 Counter Control Register (CCR0, CCR1)".
Note:
The minimum pulse width required at the ZIN pin is 2T (T is the cycle of the peripheral clock (PCLK)).
Operation performed when the reload function is in use
When the counter underflows during counting down, the UDFF bit of the counter status register (CSR)
changes to "1". At the time of the next count-down operation after the occurrence of underflow, the value of
the reload compare register (RCR) is reloaded to the counter, which then resumes counting down. At this
time, an underflow interrupt request occurs if the UDIE bit of the counter status register (CSR) is set to "1".
changes to "1". At the time of the next count-down operation after the occurrence of underflow, the value of
the reload compare register (RCR) is reloaded to the counter, which then resumes counting down. At this
time, an underflow interrupt request occurs if the UDIE bit of the counter status register (CSR) is set to "1".
Figure 6-3 shows the operation performed when the reload function is in use.
MB91520 Series
MN705-00010-1v0-E
1032