Fujitsu FR81S User Manual
CHAPTER 28: REAL-TIME CLOCK(RTC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: REAL-TIME CLOCK(RTC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
11
4.2. Sub-second Register : WTBR
The bit configuration of the sub-second register is shown below.
This register contains the reload value of the sub-second counter (22-bit down counter).
WTBRH : Address 0565
H
(Access: Byte)
WTBRM : Address 0566
H
(Access: Byte)
WTBRL : Address 0567
H
(Access: Byte)
WTBRH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
D21
D20
D19
D18
D17
D16
Initial value
-
-
X
X
X
X
X
X
Attribute R1,WX
R1,WX
R/W
R/W
R/W
R/W
R/W
R/W
WTBRM
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
X
X
X
X
X
X
X
X
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WTBRL
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
X
X
X
X
X
X
X
X
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register will be initialized by all reset source without the reset return from watch mode (power
shut-down).
The sub-second register contains the reload value used in the sub-second counter(22-bit down counter).
This value will be reloaded as soon as the sub-second counter (22-bit down counter) becomes "0". To modify
the sub-second register, confirm that no reload operations are being performed during the writing instruction.
Otherwise, the sub-second counter (22-bit down counter) will load a wrong value that combines both new and
old data bytes. Generally, it is recommended to perform update while the ST bit is "0". While the sub-second
register is set to "0", the sub-second counter(22-bit down counter) will not run at all.
The sub-second register settings for counting 0.5 second are as follows:
MB91520 Series
MN705-00010-1v0-E
1050